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www.motorola.com/semiconductors m68hc05 microcontrollers MC68HC05C8A/d rev. 5, 4/2002 MC68HC05C8A mc68hcl05c8a technical data mc68hsc05c8a

MC68HC05C8A ? mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola 3 MC68HC05C8A mc68hcl05c8a mc68hsc05c8a technical data to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://www.motorola.com/semiconductors/ the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. motorola and the stylized m logo are registered trademarks of motorola, inc. digitaldna is a trademark of motorola, inc. ? motorola, inc., 2002
technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 4 motorola revision history revision history date revision level description page number(s) april, 2002 5.0 corrected world wide web address and qualification status n/a
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola list of sections 5 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 19 section 2. memory mory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 section 3. central processor unit (cpu) . . . . . . . . . . . . 37 section 4. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 section 5. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 section 6. low-power modes. . . . . . . . . . . . . . . . . . . . . . 51 section 7. input/output (i/o) ports /output (i/o) ports . . . . . . . . . . . . . . . . . 55 section 8. timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 section 9. serial communications interface (sci) . . . . . 69 section 10. serial peripheral interface (spi). . . . . . . . . . 87 section 11. operating modes. . . . . . . . . . . . . . . . . . . . . . 97 section 12. 2. instruction set . . . . . . . . . . . . . . . . . . . . . . . 103 section 13. electrical specifications. . . . . . . . . . . . . . . 121 section 14. mechanical specifications . . . . . . . . . . . . . 137 section 15. ordering information . . . . . . . . . . . . . . . . . 141 appendix a. mc68hcl05c8a hcl05c8a . . . . . . . . . . . . . . . . . . . . 145 appendix b. mc68hsc05c8a . . . . . . . . . . . . . . . . . . . . 149 appendix c. m68hc05cx family feature comparisons . . . . . . . . . . . . . . . . . . . . . 155
list of sections technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 6 list of sections motorola
MC68HC05C8A ? mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola table of contents 7 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.2 irq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.3 osc1 and osc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.5 tcap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.6 tcmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.5.7 port a (pa0?pa7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.8 port b (pb0?pb7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.9 port c (pc0?pc7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.10 port d (pd0?pd5 and pd7). . . . . . . . . . . . . . . . . . . . . . . . . 27 section 2. memory 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3 read-only memory (rom). . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.4 rom security feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.5 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . . 30
table of contents technical data MC68HC05C8A ? mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 8 table of contents motorola section 3. central processor unit (cpu) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.3 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.4 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 section 4. interrupts 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.3 hardware controlled interrupt sequence . . . . . . . . . . . . . . . . . 43 4.4 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.5 external interrupt (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.6 timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.7 serial communications interrupt (sci) . . . . . . . . . . . . . . . . . . . 45 4.8 serial peripheral interrupt (spi) . . . . . . . . . . . . . . . . . . . . . . . .46 section 5. resets 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.4 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5 computer operating properly (cop) reset . . . . . . . . . . . . . . . 48 5.5.1 resetting the cop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5.2 cop during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.5.3 cop during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.5.4 cop during self-check mode . . . . . . . . . . . . . . . . . . . . . . . 49
table of contents MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola table of contents 9 section 6. low-power modes 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.4 stop recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.5 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 section 7. input/output (i/o) ports 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.7 input/output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 section 8. timer mer 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.3 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.4 output compare register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.5 input capture register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 8.6 timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 8.7 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8.8 timer during wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.9 timer during stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
table of contents technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 10 table of contents motorola section 9. serial communications interface (sci) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.4 sci data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.5 sci operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.5.1 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.5.1.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.5.1.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.5.1.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.5.1.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.5.1.5 transmitter interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . .74 9.5.2 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.5.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.5.2.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.5.2.3 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.5.2.4 receiver noise immunity . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.5.2.5 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.5.2.6 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.6 sci input/output (i/o) registers. . . . . . . . . . . . . . . . . . . . . . . . 78 9.6.1 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.6.2 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.6.3 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.6.4 sci status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.6.5 baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 section 10. serial peripheral interface (spi) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.4 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 10.4.1 master in slave out (miso) . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.4.2 master out slave in (mosi) . . . . . . . . . . . . . . . . . . . . . . . . . 88
table of contents MC68HC05C8A ? mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola table of contents 11 10.4.3 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.4.4 slave select (ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 10.6 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 10.6.1 serial peripheral control register . . . . . . . . . . . . . . . . . . . . 93 10.6.2 serial peripheral status register . . . . . . . . . . . . . . . . . . . . .94 10.6.3 serial peripheral data i/o register . . . . . . . . . . . . . . . . . . . 96 section 11. operating modes 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.3 user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.4 self-check mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.4.1 self-check tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.4.2 self-check results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 section 12. instruction set 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.2 immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.6 indexed, 8-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.7 indexed, 16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.4.1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . 108 12.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . 109 12.4.3 jump/branch instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . .112
table of contents technical data MC68HC05C8A ? mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 12 table of contents motorola 12.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 12.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.6 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 section 13. electrical specifications 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 13.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 13.4 operating temperature range. . . . . . . . . . . . . . . . . . . . . . . . 122 13.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.6 power considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.7 5.0-v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . 125 13.8 3.3-v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . 126 13.9 5.0-v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.10 3.3-v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 13.11 5.0-v serial peripheral interface timing . . . . . . . . . . . . . . . 132 13.12 3.3-v serial peripheral interface timing . . . . . . . . . . . . . . . 133 section 14. mechanical specifications 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 14.3 40-pin plastic dual in-line (dip) package (case 711-03) . . . 138 14.4 42-pin plastic shrink dual in-line (sdip) package (case 858-01). . . . . . . . . . . . . . . . . . . . . . . . . . .138 14.5 44-lead plastic leaded chip carrier (plcc) (case 777-02). 139 14.6 44-lead quad flat pack (qfp) (case 824a-01) . . . . . . . . . . 140
table of contents MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola table of contents 13 section 15. ordering information 5. ordering information 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 15.3 mcu ordering forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 15.4 application program media. . . . . . . . . . . . . . . . . . . . . . . . . . .142 15.5 rom program verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 15.6 rom verification units (rvus). . . . . . . . . . . . . . . . . . . . . . . . 143 appendix a. mc68hcl05c8a a.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 a.3 low-power operating temperature range . . . . . . . . . . . . . . 145 a.4 2.5-v to 3.6-v dc electrical characteristics . . . . . . . . . . . . . 146 a.5 1.8-v to 2.4-v dc electrical characteristics . . . . . . . . . . . . . . 146 a.6 low-power supply current . . . . . . . . . . . . . . . . . . . . . . . . . . 147 appendix b. mc68hsc05c8a b.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 b.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 b.3 high-speed operating temperature range. . . . . . . . . . . . . . 149 b.4 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 150 b.5 4.5-v to 5.5-v control timing . . . . . . . . . . . . . . . . . . . . . . . . . 151 b.6 2.4-v to 3.6-v control timing . . . . . . . . . . . . . . . . . . . . . . . . . 152 b.7 4.5-v to 5.5-v high-speed spi timing . . . . . . . . . . . . . . . . . . 153 b.8 2.4-v to 3.6-v high-speed spi timing . . . . . . . . . . . . . . . . . . 154 appendix c. m68hc05cx family feature comparisons
table of contents ble of contents technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 14 table of contents motorola
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola list of figures 15 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a list of figures figure title page 1-1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1-2 40-pin dual in-line package . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1-3 42-pin plastic shrink dual in-line package . . . . . . . . . . . . . . . 24 1-4 44-lead plastic leaded chip carrier . . . . . . . . . . . . . . . . . . . . 25 1-5 44-lead quad flat pack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2-1 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2-2 input/output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3-1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3-2 stacking order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4-1 interrupt flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6-1 stop/wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6-2 stop recovery timing diagram . . . . . . . . . . . . . . . . . . . . . . . .53 7-1 port b pullup option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7-2 i/o circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8-1 timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8-2 output compare operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8-3 input capture operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8-4 timer control register (tcr). . . . . . . . . . . . . . . . . . . . . . . . . . 65 8-5 timer status register (tsr) . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9-1 sci data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9-2 sci transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9-3 sci receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
list of figures technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 16 list of figures motorola figure title page 9-4 sci data register (scdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 9-5 sci control register 1 (sccr1) . . . . . . . . . . . . . . . . . . . . . . . 79 9-6 sci control register 2 (sccr2) . . . . . . . . . . . . . . . . . . . . . . . 80 9-7 sci status register (scsr). . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9-8 baud rate register (baud) . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 10-1 data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10-2 serial peripheral interface block diagram . . . . . . . . . . . . . . . . 91 10-3 serial peripheral interface master-slave interconnection . . . . 92 10-4 spi control register (spcr) . . . . . . . . . . . . . . . . . . . . . . . . . . 93 10-5 spi status register (spsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10-6 spi data register (spsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11-1 user mode pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 11-2 self-check circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . 101 13-1 test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13-2 maximum supply current versus internal clock frequency, v dd = 5.5 v . . . . . . . . . . . . . . . 127 13-3 maximum supply current versus internal clock frequency, v dd = 3.6 v . . . . . . . . . . . . . . . 127 13-4 tcap timing relationships . . . . . . . . . . . . . . . . . . . . . . . . . . 129 13-5 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13-6 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 13-7 stop recovery timing diagram . . . . . . . . . . . . . . . . . . . . . . 131 13-8 power-on reset timing diagram. . . . . . . . . . . . . . . . . . . . . . 131 13-9 spi master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 134 13-10 spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola list of tables 17 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a list of tables table title page 4-1 vector addresses for interrupts and reset. . . . . . . . . . . . . . . . 42 7-1 i/o pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9-1 baud rate generator clock prescaling . . . . . . . . . . . . . . . . . . 84 9-2 baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 9-3 baud rate selection examples . . . . . . . . . . . . . . . . . . . . . . . .86 10-1 serial peripheral rate selection. . . . . . . . . . . . . . . . . . . . . . . . 94 11-1 operating mode conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11-2 self-check circuit led codes . . . . . . . . . . . . . . . . . . . . . . . . 100 12-1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . . . . . 108 12-2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . .109 12-3 jump and branch instructions . . . . . . . . . . . . . . . . . . . . . . . . 111 12-4 bit manipulation instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 112 12-5 control instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 12-6 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12-7 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 c-1 m68hc05cx feature comparison . . . . . . . . . . . . . . . . . . . . . 156
list of tables technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 18 list of tables motorola
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola general description 19 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.2 irq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.3 osc1 and osc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.5 tcap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.6 tcmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.5.7 port a (pa0 ? pa7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.8 port b (pb0 ? pb7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.9 port c (pc0 ? pc7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.10 port d (pd0 ? pd5 and pd7). . . . . . . . . . . . . . . . . . . . . . . . . 27 1.2 introduction the MC68HC05C8A is an enhanced version of the mc68hc05c8. it includes keyboard scanning logic, a high current pin, a computer operating properly (cop) watchdog timer, and read-only memory (rom) security feature.
general description ption technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 20 general description motorola 1.3 features m68hc05 core single 3.0- to 5.5-volt supply available packages: ? 40-pin dual in-line (dip) ? 42-pin plastic shrink dual in-line (sdip) ? 44-lead plastic leaded chip carrier (plcc) ? 44-lead quad flat pack (qfp) on-chip oscillator for crystal/ceramic resonator fully static operation 7744 bytes of user rom rom security feature 176 bytes of on-chip random-access memory (ram) asynchronous serial communications interface (sci) system synchronous serial peripheral interface (spi) system 16-bit capture/compare timer system computer operating properly (cop) watchdog timer 24 bidirectional input/output (i/o) lines seven input-only lines user mode self-check mode power-saving stop and wait modes high current sink and source on one port pin (pc7) mask selectable external interrupt sensitivity mask-programmable keyscan logic
general description features MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola general description 21 figure 1-1. block diagram tcap 2 accumulator index register stack pointer program counter condition code register osc1 osc2 oscillator internal reset irq cop cpu m68hc05 cpu alu v dd v ss cpu registers control port a data direction a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 processor clock power sram ? 176 bytes user rom and user vectors ? 7744 bytes self-check rom ? 240 bytes system 1 1 0 0 0 0 0 0 0 0 c z n i h 1 1 1 16-bit capture/compare port b data direction b pb0* pb1* pb2* pb3* pb4* pb5* pb6* pb7* port c data direction c pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 ? ?? timer system baud rate generator pd7 rdi(pd0) tdo(pd1) miso(pd2) mosi(pd3) sck(pd4) ss (pd5) port d sci spi baud rate generator tcmp * port b pins also function as external interrupts. ? pc7 has a high current sink and source capability.
general description technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 22 general description motorola 1.4 mask options eight mask options are available to select the pullup/interrupts on port b on a pin-by-pin basis. there are also four mask options for: 1. irq (edge-sensitive only or edge- and level-sensitive) 2. clock (crystal or rc) 3. cop (enable or disable) 4. stop (enable or disable). 1.5 functional pin description the MC68HC05C8A is available in a 40-pin dip (see figure 1-2 ), 42-pin sdip (see figure 1-3 ), 44-pin plcc (see figure 1-4 ), and 44-pin qfp (see figure 1-5 ). the following paragraphs describe the general function of each pin. note: a line over a signal name indicates an active low signal. for example, reset is active high and reset is active low. any reference to voltage, current, resistance, capacitance, time, or frequency specified in the following paragraphs will refer to the nominal values. the exact values and their tolerance or limits are specified in section 13. electrical specifications .
general description functional pin description MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola general description 23 figure 1-2. 40-pin dual in-line package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 28 29 30 31 32 33 34 35 36 37 38 39 40 v dd osc1 osc2 tcap pd7 tcmp pd5/ss pd4/sck pd3/mosi pd2/miso pd1/tdo pd0/rdi pc0 pc1 reset irq nc* pa7 pa5 pa4 pa3 pa2 pa1 pa0 pb0 pb1 pb2 pa6 15 16 17 18 19 20 pb4 pb5 pb6 pb7 v ss pb3 21 22 23 24 25 26 pc2 pc3 pc4 pc5 pc6 pc7 * if mc68hc705c8a otps are to be used in the same application, this pin should be tied to v dd .
general description technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 24 general description motorola figure 1-3. 42-pin plastic shrink dual in-line package reset irq nc* pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 pb0 pb1 pb2 pb3 nc pb4 pb5 pb6 v ss v dd osc1 osc2 tcap pd7 tcmp pd5/ss pd4/sck pd3/mosi pd2/miso pd1/tdo pd0/rdi pc0 pc1 pc2 nc pc3 pc4 pc5 pc6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 pc7 pb7 21 * if mc68hc705c8a otps are to be used in the same application, this pin should be tied to v dd .
general description functional pin description MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola general description 25 figure 1-4. 44-lead plastic leaded chip carrier figure 1-5. 44-lead quad flat pack pa6 pa7 nc* nc irq reset v dd osc1 osc2 tcap nc 6 5 4 3 2 1 44 43 42 41 40 39 38 37 pd7 tcmp pd5/ss 36 35 pd4/sck pd3/mosi 34 pd2/miso 33 pd1/tdo 32 pd0/rdi 31 pc0 30 pc1 29 pc2 28 27 26 25 24 23 22 21 20 19 18 nc pb5 pb6 pb7 v ss nc pc7 pc6 pc5 pc4 pc3 pb4 pb3 pb2 pb1 17 16 15 14 pb0 pa0 pa1 pa2 13 12 11 10 pa3 9 pa4 8 pa5 7 * if mc68hc705c8a otps are to be used in the same application, this pin should be tied to v dd . pd7 tcap osc2 osc1 v dd nc nc reset irq nc* pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 pb0 pb1 pb2 pb3 pd3/mosi pd2/miso pd4/sck pd5/ss tcmp pd1/tdo pd0/rdi pc0 pc1 pc2 pc3 nc pc4 pc5 pc6 pc7 v ss nc pb7 pb6 pb5 pb4 1 234567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 * if mc68hc705c8a otps are to be used in the same application, this pin should be tied to v dd .
general description technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 26 general description motorola 1.5.1 v dd and v ss power is supplied to the microcontroller using these two pins. v dd is the positive supply and v ss is ground. 1.5.2 irq this pin has a mask selectable option that provides two different choices of interrupt triggering sensitivity. the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. refer to section 4. interrupts for more detail. 1.5.3 osc1 and osc2 these pins provide control input for an on-chip clock oscillator circuit. a crystal, a ceramic resonator, a resistor/capacitor combination, or an external signal connects to these pins providing a system clock. the internal bus rate is one-half the external oscillator frequency. 1.5.4 reset this active low pin is used to reset the mcu to a known startup state by pulling reset low. the reset pin contains an internal schmitt trigger as part of its input to improve noise immunity. 1.5.5 tcap this pin controls the input capture feature for the on-chip programmable timer. the tcap pin contains an internal schmitt trigger as part of its input to improve noise immunity. 1.5.6 tcmp the tcmp pin provides an output for the output compare feature of the on-chip timer subsystem.
general description functional pin description MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola general description 27 1.5.7 port a (pa0 ? pa7) these eight input/output (i/o) lines comprise port a. the state of any pin is software programmable and all port a lines are configured as input during power-on or reset. for detailed information on i/o programming, see 7.7 input/output programming . 1.5.8 port b (pb0 ? pb7) these eight i/o lines comprise port b. the state of any pin is software programmable, and all port b lines are configured as input during power- on or reset. port b has mask option enabled pullup devices and interrupt capability by pin. the interrupts and pullups are enabled together. for a detailed description on i/o programming, refer to 7.7 input/output programming . 1.5.9 port c (pc0 ? pc7) these eight i/o lines comprise port c. the state of any pin is software programmable and all port c lines are configured as input during power- on or reset. pc7 has high current sink and source capability. for a detailed description on i/o programming, refer to 7.7 input/output programming . 1.5.10 port d (pd0 ? pd5 and pd7) these seven port lines comprise port d. pd7 and pd5 ? pd0 are input only. pd0 and pd1 are shared with the sci subsystem and pd2 ? pd5 are shared with the spi subsystem. for a detailed description on i/o programming, refer to 7.7 input/output programming .
general description technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 28 general description motorola
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola memory 29 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a l05c8a mc68hsc05c8a section 2. memory 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3 read-only memory (rom). . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.4 rom security feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.5 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . . 30 2.2 introduction the MC68HC05C8A has an 8-kbyte memory map, consisting of user read-only memory (rom), user random-access memory (ram), self- check rom, and input/output (i/o) registers. see figure 2-1 and figure 2-2 . 2.3 read-only memory (rom) the user rom consists of 48 bytes of page zero rom from $0020 to $004f, 7680 bytes of user rom from $0100 to $1eff, and 16 bytes of user vectors from $1ff0 to $1fff. the self-check rom and vectors are located from $1f00 to $1fef. see figure 2-1. twelve of the user vectors, $1ff4 ? $1fff, are dedicated to user- defined reset and interrupt vectors. the remaining four bytes from $1ff0 ? $1ff3 are not used.
memory technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 30 memory motorola 2.4 rom security feature feature a security (1) feature has been incorporated into the MC68HC05C8A to help prevent externally reading of code in the rom. this feature aids in keeping customer developed software proprietary. 2.5 random-access memory (ram) the user ram consists of 176 bytes and is used both for general- purpose ram and stack area. the stack begins at address $00ff. the stack pointer can access 64 bytes of ram in the range $00ff to $00c0. see figure 2-1. note: using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. 1. no security feature is absolutely secure. however, motorola ? s strategy is to make reading or copying the rom difficult for unauthorized users.
memory random-access memory (ram) MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola memory 31 figure 2-1. memory map port a data register port b data register port c data register port d data register port a data direction register port b data direction register port c data direction register unused unused unused spi control register spi status register spi data register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register input capture register (high) not used (3 bytes) spi vector (high) spi vector (low) sci vector (high) sci vector (low) timer vector (high) timer vector (low) irq vector (high) irq vector (low) swi vector (high) swi vector (low) reset vector (high byte) reset vector (low byte) $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0012 $0011 $0013 $0019 $001a $001b $001c $1ff2 $1ff4 $1ff3 $1ff5 $1ff6 $1ff7 $1ff8 i/o registers 32 bytes $0000 $001f $0020 $004f $0050 ram 176 bytes $00ff $0100 user rom 7680 bytes user rom vectors $1fff 16 bytes $0014 input capture register (low) output compare register (high) output compare register (low) timer counter register (high) $1ff9 $1ffb $1ffa $1ffc $1ffd $1ffe $1fff timer counter register (low) $0015 $0016 $0017 $0018 $001d $001e $001f alternate counter register (high) alternate counter register (low) unused unused unused unused $1fef $1ff0 $1eff $1f00 (stack) 64 bytes self-check rom and vectors 240 bytes $00bf $00c0 $1ff1 $1ff0 user rom 48 bytes cop register
memory technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 32 memory motorola addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (porta) see page 56. read: pa7 pa 6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset $0001 port b data register (portb) see page 56. read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: unaffected by reset $0002 port c data register (portc) see page 57. read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: unaffected by reset $0003 port d data register (portd) see page 57. read: pd7 pd5 pd4 pd3 pd2 pd1 pd0 write: reset: unaffected by reset $0004 port a data direction register (ddra) see page 56. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0 0 0 0 0 0 0 0 $0005 port b data direction register (ddrb) see page 56. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 0 0 0 0 0 0 0 0 $0006 port c data direction register (ddrc) see page 57. read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 0 0 0 0 0 0 0 0 $0007 unimplemented $0008 unimplemented $0009 unimplemented = unimplemented r = reserved u = unaffected figure 2-2. input/output registers (sheet 1 of 4)
memory random-access memory (ram) MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola memory 33 $000a spi control register (spcr) see page 93. read: spie spe mstr cpol cpha spr1 spr0 write: reset: 0 0 0 0 0 0 u u $000b spi status register (spsr) see page 94. read: spif wcol 0 modf 0000 write: reset: 0 0 0 0 0 0 u u $000c spi data register (spdr) see page 96. read: spd7 spd6 spd5 spd4 spd31 spd2 spd1 spd0 write: reset: unaffected by reset $000d sci baud rate register baud see page 84. read: 0 0 scp1 scp0 0 scr2 scr1 scr0 write: reset: 0 0 0 0 0 u u u $000e sci control register 1 (sccr1) see page 79. read: r8 t8 0 m wake 0 0 0 write: reset: unaffected by reset $000f sci control register 2 (sccr2) see page 80. read: tie tcie rie ilie te re rmw sbk write: reset: 0 0 0 0 0 0 0 0 $0010 sci status register (scsr) see page 82. read: tdre tc rdrf idle or nf fe 0 write: reset: 0 0 0 0 0 0 0 0 $0011 sci data register (scdat) see page 78. read: scd7 sdc5 scd5 scd4 scd3 scd2 scd1 scd0 write: reset: unaffected by reset $0012 timer control register (tcr) see page 65. read: icie ocie toie 0 0 0 iedge olvl write: reset: 0 0 0 0 0 0 u 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 2-2. input/output registers (sheet 2 of 4)
memory technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 34 memory motorola $0013 timer status register (tsr) see page 66. read: icf ocf tof 0 0 0 0 0 write: reset: u u u 0 0 0 0 0 $0014 input capture register high (icr) see page 63. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset $0015 input capture register low (icr) see page 63. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $0016 output compare register high (ocr) see page 62. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset $0017 output compare register low (ocr) see page 62. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $0018 timer counter register high (tcnt) see page 61. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0019 timer counter register low (tcnt) see page 61. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $001a alternate counter register high (altcnt) see page 61. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $001b alternate counter register low (altcnt) see page 61. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 2-2. input/output registers (sheet 3 of 4)
memory random-access memory (ram) MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola memory 35 $001c unimplemented $001d unimplemented $001e unimplemented $001f reserved r r r r r r r r $1ff0 cop reset register see page 48. read: user rom data write: copc reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 2-2. input/output registers (sheet 4 of 4)
memory technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 36 memory motorola
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola central processor unit (cpu) 37 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a section 3. central processor unit (cpu) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.3 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.4 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2 introduction this section describes the central processor unit (cpu) registers. 3.3 cpu registers the five cpu registers are shown in figure 3-1 and the interrupt stacking order in figure 3-2 .
central processor unit (cpu) technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 38 central processor unit (cpu) motorola figure 3-1. programming model figure 3-2. stacking order 3.3.1 accumulator the accumulator (a) shown in figure 3-1 is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 3.3.2 index register the index register (x) is an 8-bit register used by the indexed addressing x) is an 8-bit register used by the indexed addressing value to create an effective address. the index register also may be used as a temporary storage area. a 70 x 70 hinzc ccr 11 sp 7 0 pc 12 0 accumulator index register program counter stack pointer condition code register 0 0 0 0 0 12 index register pcl accumulator condition code register pch 111 70 stack i n t e r r u p t decreasing unstack r e t u r n increasing note: since the stack pointer decrements during pushes, the pcl is stacked first, followed by pch, etc. pulling from the stack is in the reverse order. memory addresses memory addresses
central processor unit (cpu) cpu registers MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola central processor unit (cpu) 39 3.3.3 program counter the program counter (pc) is a 13-bit register that contains the address of the next byte to be fetched. 3.3.4 stack pointer the stack pointer (sp) contains the address of the next free location on the stack. during an mcu reset or the reset stack pointer (rsp) instruction, the stack pointer is set to location $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the seven most significant bits (msb) are permanently set to 0000011. these eight bits are appended to the six least significant register bits (lsb) to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses five locations. 3.3.5 condition code register the condition code register (ccr) is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. these bits can be tested individually by a program, and specific actions can be taken as a result of their state. each bit is explained here. h ? half carry this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. i ? interrupt when this bit is set, the timer and external interrupt are masked (disabled). if an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the interrupt bit is cleared.
central processor unit (cpu) technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 40 central processor unit (cpu) motorola n ? negative when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. z ? zero when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was 0. c ? carry/borrow when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit also is affected during bit test and branch instructions and during shifts and rotates.
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola interrupts 41 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a l05c8a mc68hsc05c8a section 4. interrupts 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.3 hardware controlled interrupt sequence . . . . . . . . . . . . . . . . . 43 4.4 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.5 external interrupt (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.6 timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.7 serial communications interrupt (sci) . . . . . . . . . . . . . . . . . . . 45 4.8 serial peripheral interrupt (spi) . . . . . . . . . . . . . . . . . . . . . . . .46 4.2 introduction the microcontroller unit (mcu) can be interrupted five different ways: four maskable hardware interrupts, irq (interrupt request), spi (serial peripheral interface), sci (serial communications interface), and timer non-maskable software interrupt instruction (swi) port b interrupts, if enabled, are combined with the irq to form a single interrupt source. interrupts cause the processor to save register contents on the stack and to set the interrupt mask (i bit) to prevent additional interrupts. the rti (return to interrupt) instruction causes the register contents to be recovered from the stack and normal processing to resume.
interrupts technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 42 interrupts motorola unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but they are considered pending until the current instruction is complete. note: the current instruction is the one already fetched and being operated on. when the current instruction is complete, the processor checks all pending hardware interrupts. if interrupts are not masked (ccr i bit clear) and if the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. the swi is executed the same as any other instruction, regardless of the i- bit state. vector addresses for all interrupts, including reset, are listed in table 4-1 . table 4-1. vector addresses for interrupts and reset register flag name interrupts cpu interrupt vector address n/a n/a reset reset $1ffe ? $1fff n/a n/a software swi $1ffc ? $1ffd n/a n/a external interrupt irq $1ffa ? $1ffb tsr icf timer input capture timer $1ff8 ? $1ff9 tsr ocf timer output compare timer $1ff8 ? $1ff9 tsr tof timer overflow timer $1ff8 ? $1ff9 scsr tdre transmit buffer empty sci $1ff6 ? $1ff7 scsr tc transmit complete sci $1ff6 ? $1ff7 scsr rdrf receiver buffer full sci $1ff6 ? $1ff7 scsr idle idle line detect sci $1ff6 ? $1ff7 scsr or overrun sci $1ff6 ? $1ff7 spsr spif transfer complete spi $1ff4 ? $1ff5 spsr modf mode fault spi $1ff4 ? $1ff5
interrupts hardware controlled interrupt sequence MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola interrupts 43 4.3 hardware controlled interrupt sequence three functions (reset, stop, and wait) are not in the strictest sense interrupts; however, they are acted upon in a similar manner. flowcharts for hardware interrupts are shown in figure 4-1 . 1. reset ? a low input on the reset input pin causes the program to vector to its starting address, which is specified by the contents of memory locations $1ffe and $1fff. the i bit in the condition code register is also set. much of the mcu is configured to a known state during this type of reset, as previously described in section 5. resets . 2. stop ? the stop instruction causes the oscillator to be turned off and the processor to ? sleep ? until an external interrupt ( irq) or reset occurs. 3. wait ? the wait instruction causes all processor clocks to stop, but leaves the timer clock running. this ? rest ? state of the processor can be cleared by reset, an external interrupt (irq ), serial peripheral interface, serial communications interface, or timer interrupt. these individual interrupts have no special wait vectors. 4.4 software interrupt (swi) ) the software interrupt (swi) is an executable instruction and a non- maskable interrupt. it is executed regardless of the state of the i bit in the ccr. if the i bit is 0 (interrupts enabled), swi executes after interrupts which were pending when the swi was fetched but before interrupts generated after the swi was fetched. the interrupt service routine address is specified by the contents of memory locations $1ffc and $1ffd.
interrupts technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 44 interrupts motorola figure 4-1. interrupt flowchart internal timer interrupt ? internal sci interrupt ? n restore registers from stack: ccr, a, x, pc irq external interrupt ? load pc from: swi: $1ffc-$1ffd irq : $1ffa-$1ffb timer: $1ff8-$1ff9 sci: $1ff6-$1ff7 set i bit in cc register stack pc, x, a, ccr clear irq request latch fetch next instruction execute instruction n n y y y n i bit in ccr set? internal spi interrupt ? swi instruction ? n y rti instruction ? y from reset n y n y
interrupts external interrupt (irq) MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola interrupts 45 4.5 external interrupt (irq) if the interrupt mask bit (i bit) of the ccr is set, all maskable interrupts (internal and external) are disabled. clearing the i bit enables interrupts. the interrupt request is latched immediately following the falling edge of irq . it is then synchronized internally and serviced as specified by the contents of $1ffa and $1ffb. when any of the port b pullups are enabled, that pin becomes an additional external interrupt source which is coupled to the irq pin logic. it follows the same edge/edge-level selection that the irq pin has. see figure 7-1 . port b pullup option . either a level-sensitive and edge-sensitive trigger, or an edge-sensitive- only trigger operation is selectable by mask option. note: the internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the i bit is cleared. 4.6 timer interrupt three different timer interrupt flags cause a timer interrupt whenever they are set and enabled. the interrupt flags are in the timer status register (tsr), and the enable bits are in the timer control register (tcr). any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $1ff8 and $1ff9. 4.7 serial communications interrupt (sci) five different sci interrupt flags cause an sci interrupt whenever they are set and enabled. the interrupt flags are in the sci status register (scsr), and the enable bits are in the sci control register 2 (sccr2). any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $1ff6 and $1ff7.
interrupts technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 46 interrupts motorola 4.8 serial peripheral interrupt (spi) two different spi interrupt flags cause an spi interrupt whenever they are set and enabled. the interrupt flags are in the spi status register (spsr), and the enable bits are in the spi control register (spcr). either of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $1ff4 and $1ff5.
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola resets 47 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a 05c8a mc68hcl05c8a mc68hsc05c8a section 5. resets 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.4 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5 computer operating properly (cop) reset . . . . . . . . . . . . . . . 48 5.5.1 resetting the cop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5.2 cop during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.5.3 cop during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.5.4 cop during self-check mode . . . . . . . . . . . . . . . . . . . . . . . 49 5.2 introduction the microcontroller unit (mcu) can be reset three ways: 1. initial power-on reset function 2. active low input to the reset pin 3. computer operating properly (cop) reset
resets technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 48 resets motorola 5.3 power-on reset (por) an internal reset is generated on power-up to allow the internal clock generator to stabilize. the power-on reset is strictly for power turn-on conditions and should not be used to detect a drop in the power supply voltage. there is a 4064 internal processor clock cycle (t cyc ) oscillator stabilization delay after the oscillator becomes active. if the reset pin is low after the end of this 4064-cycle delay, the mcu will remain in the reset condition until reset goes high. for additional information, refer to figure 13-8. power-on reset timing diagram . 5.4 reset t pin the mcu is reset when a logic 0 is applied to the reset input for a period of one and one-half machine cycles (t rl ). 5.5 computer operating properly (cop) reset this device includes a watchdog cop feature as a mask option. the cop is implemented with an 18-bit ripple counter. this provides a timeout period of 64 milliseconds at a bus rate of 2 mhz. if the cop should time out, a system reset will occur and the device will be re-initialized in the same fashion as a power-on reset (por) or external reset. 5.5.1 resetting the cop preventing a cop reset is done by writing a logic 0 to the copc bit. this action will reset the counter and begin the timeout period again. the copc bit is bit 0 of address $1ff0. a read of address $1ff0 will result in the user defined rom data at that location.
resets computer operating properly (cop) reset MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola resets 49 5.5.2 cop during wait mode the cop will continue to operate normally during wait mode. the software should pull the device out of wait mode periodically and reset the cop by writing to the copc bit to prevent a cop reset. 5.5.3 cop during stop mode stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. the cop counter will be reset when stop mode is entered. if a reset is used to exit stop mode, the cop counter will be reset after the 4064 cycles of delay after stop mode. if an interrupt is used to exit stop mode, the cop counter will not be reset after the 4064-cycle delay and will have that many cycles already counted when control is returned to the program. 5.5.4 cop during self-check mode the cop is disabled by hardware during self-check mode.
resets technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 50 resets motorola
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola low-power modes 51 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a l05c8a mc68hsc05c8a section 6. low-power modes 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.4 stop recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.5 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.2 introduction this section describes the two low-power modes ? stop and wait. figure 6-1 shows the sequence of events caused by the stop and wait instructions.
low-power modes technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 52 low-power modes motorola figure 6-1. stop/wait mode flowchart 6.3 stop mode the stop instruction places the microcontroller unit (mcu) in its lowest- power consumption mode. in stop mode, the internal oscillator is turned off, halting all internal processing, including timer operation. during stop mode, the tcr bits are altered to remove any pending timer interrupt request and to disable any further timer interrupts. the timer prescaler is cleared. the i bit in the condition code register is cleared to enable external interrupts. all other registers and memory remain 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine y stop oscillator active timer clock active processor clocks stopped clear i bit (irq ) external reset reset turn on oscillator wait for time delay to stabilize restart processor clock wait stop oscillator and all clocks clear i bit interrupt timer interrupt (irq ) external y y y y n n n n n interrupt sci y n interrupt spi n interrupt
low-power modes stop recovery MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola low-power modes 53 unaltered. all input/output lines remain unchanged. the processor can be brought out of stop mode only by an external interrupt or reset. 6.4 stop recovery the processor can be brought out of stop mode only by an external interrupt or reset. see figure 6-2 . 6.5 wait mode wait mode the wait instruction places the mcu in a low-power consumption mode, but the wait mode consumes more power than the stop mode. all cpu action is suspended, but the timer, serial communications interface (sci), serial peripheral interface (spi), and the oscillator remain active. any interrupt or reset will cause the mcu to exit wait mode. during wait mode, the i bit in the ccr is cleared to enable interrupts. all other registers, memory, and input/output lines remain in their previous state. the timer may be enabled to allow a periodic exit from wait mode. figure 6-2. stop recovery timing diagram 1ffe 1ffe 1ffe 1ffe 1fff internal address bus internal clock irq (3) irq (2) reset osc1 (1) t ilch 4064 t cyc reset ($1ffe, $1fff) or interrupt ($1ffa, $1ffb) vector fetch t ilih t rl notes: 1. represents the internal gating of the osc1 pin 2. irq pin edge-sensitive option 3. irq pin level and edge sensitive option
low-power modes technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 54 low-power modes motorola
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola input/output (i/o) ports 55 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a section 7. input/output (i/o) ports 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.7 input/output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 7.2 introduction the MC68HC05C8A has three 8-bit input/output (i/o) ports.these 24 port pins are programmable as either inputs or outputs under software control of the data direction registers. port d does not have a data direction register, and its seven pins are input only with the exception of certain serial communications (sci)/serial peripheral interface (spi) functions. note: to avoid a glitch on the output pins, write data to the i/o port data register before writing a 1 to the corresponding data direction register.
input/output (i/o) ports put/output (i/o) ports technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 56 input/output (i/o) ports motorola 7.3 port a port a is an 8-bit bidirectional port which does not share any of its pins with other subsystems. the port a data register is at $0000 and the data direction register (ddr) is at $0004. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a 1 to a ddr bit sets the corresponding port bit to output mode. 7.4 port b port b is an 8-bit bidirectional port. the port b data register is at $0001 and the data direction register (ddr) is at $0005. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a 1 to a ddr bit sets the corresponding port pin to output mode. each of the port b pins has a mask programmable interrupt capability. this interrupt option also enables a pullup device when the pin is configured as an input (see figure 7-1 ). the edge or edge and level sensitivity of the irq pin also will pertain to the enabled port b pins via mask options. be careful when using port b pins that have the pullup enabled. before switching from an output to an input, the data should be preconditioned to a 1 to prevent an interrupt from occurring. figure 7-1. port b pullup option pb0 v dd v dd ddr bit normal port circuitry as shown in from all other port b pins irq schmitt trigger to interrupt logic mask option figure 7-2
input/output (i/o) ports port c MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola input/output (i/o) ports 57 7.5 port c port c is an 8-bit bidirectional port. the port c data register is at $0002 and the data direction register (ddr) is at $0006. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a 1 to a ddr bit sets the corresponding port bit to output mode. pc7 has a high current sink and source capability. 7.6 port d port d is a 7-bit fixed input port. four of its pins are shared with the spi subsystem, two more are shared with the sci subsystem. reset does not affect the data registers. during reset, all seven bits become valid input ports because all special function output drivers associated with the sci, timer, and spi subsystems are disabled. 7.7 input/output programming i/o port pins may be programmed as inputs or outputs under software control. the direction of the pins is determined by the state of the corresponding bit in the port data direction register (ddr). each i/o port has an associated ddr. any i/o port pin is configured as an output if its corresponding ddr bit is set to a logic 1. a pin is configured as an input if its corresponding ddr bit is cleared to a logic 0. at power-on or reset, all ddrs are cleared, which configures all i/o pins as inputs. the data direction registers are capable of being written to or read by the processor. during the programmed output state, a read of the data register actually reads the value of the output data latch and not the i/o pin. for further information, refer to table 7-1 and figure 7-2 .
input/output (i/o) ports technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 58 input/output (i/o) ports motorola figure 7-2. i/o circuitry table 7-1. i/o pin functions r/w (1) 1. r/w is an internal signal. ddr i/o pin function 00 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch and output to the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in an output mode. the output data latch is read. read ddrx write ddrx reset write portx read portx internal data bus port x data data direction register x bit register bit (latched output) i/o pin [1] [2] [3] [1] this output buffer enables the latched output to drive the pin when ddr bit is 1 (output mode). [2] this input buffer is enabled when ddr bit is 0 (input mode). [3] this input buffer is enabled when ddr bit is 1 (output mode).
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola timer 59 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a hc05c8a mc68hcl05c8a mc68hsc05c8a section 8. timer 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.3 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.4 output compare register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.5 input capture register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 8.6 timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 8.7 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8.8 timer during wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.9 timer during stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.2 introduction the timer consists of a 16-bit, software-programmable counter driven by a fixed divide-by-four prescaler. this timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. pulse widths can vary from several microseconds to many seconds. refer to figure 8-1 for a timer block diagram. because the timer has a 16-bit architecture, each specific functional segment (capability) is represented by two registers. these registers contain the high and low byte of that functional segment. generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed.
timer technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 60 timer motorola note: the i bit in the condition code register should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does not occur. figure 8-1. timer block diagram input capture register clock internal bus output compare register high byte low byte $16 $17 4 internal processor 16-bit free running counter counter alternate register 8-bit buffer high byte low byte $1a $1b $18 $19 high byte low byte $14 $15 output compare circuit overflow detect circuit edge detect circuit timer status register icf ocf tof $13 icie iedg olvl output level register reset timer control register $12 output level (tcmp) interrupt circuit toie ocie edge input (tcap) d clk c q
timer counter MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola timer 61 8.3 counter the key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. the prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 mhz. the counter is incremented during the low portion of the internal bus clock. software can read the counter at any time without affecting its value. the double-byte, free-running counter can be read from either of two locations, $18, $19 (counter register) or $1a, $1b (counter alternate register). a read from only the least significant byte (lsb) of the free- running counter ($19, $1b) receives the count value at the time of the read. if a read of the free-running counter or counter alternate register first addresses the most significant byte (msb) ($18, $1a), the lsb ($19, $1b) is transferred to a buffer. this buffer value remains fixed after the first msb read, even if the user reads the msb several times. this buffer is accessed when reading the free-running counter or counter alternate register lsb ($19 or $1b) and, thus, completes a read sequence of the total counter value. in reading either the free-running counter or counter alternate register, if the msb is read, the lsb must also be read to complete the sequence. the counter alternate register differs from the counter register in one respect: a read of the counter register msb can clear the timer overflow flag (tof). therefore, the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the tof. the free-running counter is configured to $fffc during reset and is always a read-only register. during a power-on reset, the counter is also preset to $fffc and begins running after the oscillator start-up delay. because the free-running counter is 16 bits preceded by a fixed divide- by-four prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. when the counter rolls over from $ffff to $0000, the tof bit is set. an interrupt can also be enabled whenever counter rollover occurs by setting its interrupt enable bit (toie).
timer technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 62 timer motorola 8.4 output compare register the 16-bit output compare register is made up of two 8-bit registers at locations $16 (msb) and $17 (lsb). the output compare register is used for several purposes, such as indicating when a period of time has elapsed. all bits are readable and writable and are not altered by the timer hardware or reset. if the compare function is not needed, the two bytes of the output compare register can be used as storage locations. the output compare register contents are compared with the contents of the free-running counter continually, and if a match is found, the corresponding output compare flag (ocf) bit is set and the corresponding output level (olvl) bit is clocked to an output level register. the output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed timeout. an interrupt also can accompany a successful output compare, provided the corresponding interrupt enable bit (ocie) is set. after a processor write cycle to the output compare register containing the msb ($16), the output compare function is inhibited until the lsb ($17) is written also. the user must write both bytes (locations) if the msb is written first. a write made only to the lsb ($17) will not inhibit the compare function. the free-running counter is updated every four internal bus clock cycles. the minimum time required to update the output compare register is a function of the program rather than the internal hardware. the processor can write to either byte of the output compare register without affecting the other byte. the output level (olvl) bit is clocked to the output level register regardless of whether the output compare flag (ocf) is set or clear. figure 8-2 shows the logic of the output compare function.
timer input capture register MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola timer 63 figure 8-2. output compare operation 8.5 input capture register two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. the level transition which triggers the counter transfer is defined by the corresponding input edge bit (iedg). reset does not affect the contents of the input capture register except when exiting stop mode. the result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronization. resolution is one count of the free-running counter, which is four internal bus clock cycles. the free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (icf) is set or clear. the input capture register always contains the free-running counter value that corresponds to the most recent input capture. 16-bit comparator output compare register high output compare register low counter high byte tcmp pin control logic timer interrupt request counter low byte 15 0 15 8 7 0 timer status register $0013 timer control register $0012 icie ocie toie icf ocf tof
timer technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 64 timer motorola after a read of the input capture register ($14) msb, the counter transfer is inhibited until the lsb ($15) is also read. this characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. a read of the input capture register lsb ($15) does not inhibit the free- running counter transfer, since they occur on opposite edges of the internal bus clock. figure 8-3 shows the logic of the input capture function. figure 8-3. input capture operation input capture register high input capture register low timer register high tcmp edge select/detect logic timer interrupt request timer register low 15 0 15 8 7 0 timer status register $0013 timer control register $0012 icie ocie toie icf ocf tof 87 $0018 $0019 $0014 $0015 iedg latch
timer timer control register MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola timer 65 8.6 timer control register l register the timer control register (tcr) is a read/write register containing five control bits. three bits control interrupts associated with the timer status register flags icf, ocf, and tof. icie ? input capture interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled ocie ? output compare interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled toie ? timer overflow interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled iedg ? input edge bit value of input edge determines which level transition on tcap pin will trigger free-running counter transfer to the input capture register. 1 = positive edge 0 = negative edge reset does not affect the iedg bit. olvl ? output level bit value of output level is clocked into output level register by the next successful output compare and will appear on the tcmp pin. 1 = high output 0 = low output address: $0012 bit 7654321bit 0 read: icie ocie toie 0 0 0 iedg olvl write: reset:000000u0 u = unaffected figure 8-4. timer control register (tcr)
timer technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 66 timer motorola bits 2, 3, and 4 ? not used always read 0 8.7 timer status register the timer status register (tsr) is a read-only register containing three status flag bits. icf ? input capture flag 1 = flag set when selected polarity edge is sensed by input capture edge detector 0 = flag cleared when tsr and input capture low register ($15) are accessed ocf ? output compare flag 1 = flag set when output compare register contents match the free- running counter contents 0 = flag cleared when tsr and output compare low register ($17) are accessed tof ? timer overflow flag 1 = flag set when free-running counter transition from $ffff to $0000 occurs 0 = flag cleared when tsr and counter low register ($19) are accessed bits 0 ? 4 ? not used always read 0 address: $0013 bit 7654321bit 0 read: icf ocf tof 00000 write: reset:uuu00000 = unimplemented u = unaffected figure 8-5. timer status register (tsr)
timer timer during wait mode MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola timer 67 accessing the timer status register satisfies the first condition required to clear status bits. the remaining step is to access the register corresponding to the status bit. a problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: 1. the timer status register is read or written when tof is set. 2. the lsb of the free-running counter is read but not for the purpose of servicing the flag. the counter alternate register at addresses $1a and $1b contains the same value as the free-running counter (at address $18 and $19); therefore, this alternate register can be read at any time without affecting the timer overflow flag in the timer status register. 8.8 timer during wait mode the central processor unit (cpu) clock halts during wait mode, the timer remains active. if interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode. 8.9 timer during stop mode in stop mode, the timer stops counting and holds the last count value if stop is exited by an interrupt. if reset is used, the counter is forced to $fffc. during stop, if at least one valid input capture edge occurs at the tcap pin, the input capture detect circuit is armed. this does not set any timer flags or wake up the microcontroller unit (mcu). but if the mcu exits stop due to an external interrupt, there is an active input capture flag and data from the first valid edge that occurred during the stop mode. if reset is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred.
timer technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 68 timer motorola
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola serial communications interface (sci) 69 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a mc68hcl05c8a mc68hsc05c8a section 9. serial communications interface (sci) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.4 sci data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.5 sci operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.5.1 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.5.1.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.5.1.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.5.1.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.5.1.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.5.1.5 transmitter interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . .74 9.5.2 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.5.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.5.2.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.5.2.3 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.5.2.4 receiver noise immunity . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.5.2.5 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.5.2.6 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.6 sci input/output (i/o) registers. . . . . . . . . . . . . . . . . . . . . . . . 78 9.6.1 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.6.2 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.6.3 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.6.4 sci status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.6.5 baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
serial communications interface (sci) technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 70 serial communications interface (sci) motorola 9.2 introduction the serial communications interface (sci) module allows high-speed asynchronous communication with peripheral devices and other microcontroller units (mcu). 9.3 features features of the sci module include: standard mark/space non-return-to-zero format full duplex operation 32 programmable baud rates programmable 8-bit or 9-bit character length separately enabled transmitter and receiver two receiver wakeup methods: ? idle line wakeup ? address mark wakeup interrupt-driven operation capability with five interrupt flags: ? transmitter data register empty ? transmission complete ? receiver data register full ? receiver overrun ? idle receiver input receiver framing error detection 1/16 bit-time noise detection
serial communications interface (sci) sci data format MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola serial communications interface (sci) 71 9.4 sci data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 9-1 . figure 9-1. sci data format 9.5 sci operation the sci allows full-duplex, asynchronous, rs232 or rs422 serial communication between the mcu and remote devices, including other mcus. the sci ? s transmitter and receiver operate independently, although they use the same baud-rate generator. this subsection describes the operation of the sci transmitter and receiver. 9.5.1 transmitter figure 9-2 shows the structure of the sci transmitter. 9.5.1.1 character length the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (sccr1) determines character length. when transmitting 9-bit data, bit t8 in sccr1 is the ninth bit (bit 8). 8-bit data format (bit m in sccr1 clear) 9-bit data format (bit m in sccr1 set) start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 stop bit next start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 start bit stop bit next start bit
serial communications interface (sci) technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 72 serial communications interface (sci) motorola 9.5.1.2 character transmission during transmission, the transmit shift register shifts a character out to the pd1/tdo pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift register. writing a logic 1 to the te bit in sci control register 2 (sccr2) and then writing data to the scdr begins the transmission. at the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s. after the preamble shifts out, the control logic transfers the scdr data into the shift register. a logic 0 start bit automatically goes into the least significant bit position of the shift register, and a logic 1 stop bit goes into the most significant bit position. when the data in the scdr transfers to the transmit shift register, the transmit data register empty (tdre) flag in the sci status register (scsr) becomes set. the tdre flag indicates that the scdr can accept new data from the internal data bus. when the shift register is not transmitting a character, the pd1/tdo pin goes to the idle condition, logic 1. if software clears the te bit during the idle condition, and while tdre is set, the transmitter relinquishes control of the pd1/tdo pin. 9.5.1.3 break characters writing a logic 1 to the sbk bit in sccr2 loads the shift register with a k bit in sccr2 loads the shift register with a break character. a break character contains all logic 0s and has no start and stop bits. break character length depends on the m bit in sccr1. as long as sbk is at logic 1, transmitter logic continuously loads break characters into the shift register. after software clears the sbk bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. the automatic logic 1 at the end of a break character is to guarantee the recognition of the start bit of the next character.
serial communications interface (sci) sci operation MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola serial communications interface (sci) 73 figure 9-2. sci transmitter 0 t8 scdr ($0011) 6 bit 7 5 4321bit 0 baud rate register (baud) scp0 scr2 scr1 $000d r8 sci control register 1 (sccr1) m wake $000e tcie tie sci control register 2 (sccr2) rie ilie te re rwu sbk $000f scp1 tc tdre sci status register (scsr) rdrf idlr or nf $0010 bit 6 bit 7 sci data register (scdr) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0011 fe 0 transmit shift register 7 6 5 4 3 2 1 0 8 h l transmitter control logic load from scdr shift enable preamble (all logic 1s) break (all logic 0s) tdre tc m t8 te pin buffer and control pd1/ tdo internal data bus sbk tie tcie sci receive requests sci interrupt request 1x baud rate clock 0 0 0 0 0 scr0 0
serial communications interface (sci) technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 74 serial communications interface (sci) motorola 9.5.1.4 idle characters an idle character contains all logic 1s and has no start or stop bits. idle character length depends on the m bit in sccr1. the preamble is a synchronizing idle character that begins every transmission. clearing the te bit during a transmission relinquishes the pd1/tdo pin after the last character to be transmitted is shifted out. the last character may already be in the shift register, or waiting in the scdr, or in a break character generated by writing to the sbk bit. toggling te from logic 0 to logic 1 while the last character is in transmission generates an idle character (a preamble) that allows the receiver to maintain control of the pd1/tdo pin. 9.5.1.5 transmitter interrupts two sources can generate sci transmitter interrupt requests: 1. transmit data register empty (tdre) ? the tdre bit in the scsr indicates that the scdr has transferred a character to the transmit shift register. tdre is a source of sci interrupt requests. the transmission complete interrupt enable bit (tcie) in sccr2 is the local mask for tdre interrupts. 2. transmission complete (tc) ? the tc bit in the scsr indicates that both the transmit shift register and the scdr are empty and that no break or idle character has been generated. tc is a source of sci interrupt requests. the transmission complete interrupt enable bit (tcie) in sccr2 is the local mask for tc interrupts. 9.5.2 receiver figure 9-3 shows the structure of the sci receiver.
serial communications interface (sci) sci operation MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola serial communications interface (sci) 75 figure 9-3. sci receiver t8 scdr ($0011) 6 bit 7 54321bit 0 baud rate register (baud) scp0 scr2 scr1 scr0 $000d r8 sci control register 1 (sccr1) m wake $000e tcie tie sci control register 2 (sccr2) rie ilie te re rwu sbk $000f scp1 tc tdre sci status register (scsr) rdrf idlr or nf $0010 bit 6 bit 7 sci data register (scdr) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0011 fe 0 receive shift register 7 6 5 4 3 2 1 0 8 rdrf idle r8 re pin buffer and control pd0/ rdi internal data bus m rie ilie sci transmit requests sci interrupt request 16x baud rate clock data recovery wakeup logic full overrun idle msb stop start 3 16 fe rwu nf or rie 0 0 0 0 0 0 0
serial communications interface (sci) technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 76 serial communications interface (sci) motorola 9.5.2.1 character length the receiver can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (sccr1) determines character length. when receiving 9-bit data, bit r8 in sccr1 is the ninth bit (bit 8). 9.5.2.2 character reception during reception, the receive shift register shifts characters in from the pd0/rdi pin. the sci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive shift register, the data portion of the character is transferred to the scdr, setting the receive data register full (rdrf) flag. the rdrf flag can be used to generate an interrupt. 9.5.2.3 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup enable (rwu) bit in sci control register 2 (sccr2) puts the receiver into a standby state during which receiver interrupts are disabled. either of two conditions on the pd0/rdi pin can bring the receiver out of the standby state: 1. idle input line condition ? if the pd0/rdi pin is at logic 1 long enough for 10 or 11 logic 1s to shift into the receive shift register, receiver interrupts are again enabled. 2. address mark ? if a logic 1 occurs in the most significant bit position of a received character, receiver interrupts are again enabled. the state of the wake bit in sccr1 determines which of the two conditions wakes up the mcu.
serial communications interface (sci) sci operation MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola serial communications interface (sci) 77 9.5.2.4 receiver noise immunity the data recovery logic samples each bit 16 times to identify and verify the start bit and to detect noise. any conflict between noise-detection samples sets the noise flag (nf) in the scsr. the nf bit is set at the same time that the rdrf bit is set. 9.5.2.5 framing errors if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error (fe) bit in the scsr. the fe bit is set at the same time that the rdrf bit is set. 9.5.2.6 receiver interrupts three sources can generate sci receiver interrupt requests: 1. receive data register full (rdrf) ? the rdrf bit in the scsr indicates that the receive shift register has transferred a character to the scdr. 2. receiver overrun (or) ? the or bit in the scsr indicates that the receive shift register shifted in a new character before the previous character was read from the scdr. 3. idle input (idle) ? the idle bit in the scsr indicates that 10 or 11 consecutive logic 1s shifted in from the pd0/rdi pin.
serial communications interface (sci) technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 78 serial communications interface (sci) motorola 9.6 sci input/output (i/o) registers these i/o registers control and monitor sci operation: sci data register (scdr) sci control register 1 (sccr1) sci control register 2 (sccr2) sci status register (scsr) 9.6.1 sci data register the sci data register is the buffer for characters received and for characters transmitted. 9.6.2 sci control register 1 sci control register 1 has these functions: stores ninth sci data bit received and ninth sci data bit transmitted controls sci character length controls sci wakeup method address: $0011 bit 7654321bit 0 read: scd7 sdc5 scd5 scd4 scd3 scd2 scd1 scd0 write: reset: unaffected by reset figure 9-4. sci data register (scdr)
serial communications interface (sci) sci input/output (i/o) registers MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola serial communications interface (sci) 79 r8 ? bit 8 (received) when the sci is receiving 9-bit characters, r8 is the ninth bit of the received character. r8 receives the ninth bit from the receive shift register at the same time that the scdr receives the other eight bits. reset has no effect on the r8 bit. t8 ? bit 8 (transmitted) when the sci is transmitting 9-bit characters, t8 is the ninth bit of the transmitted character. t8 is loaded into the transmit shift register at the same time that scdr is loaded into the transmit shift register. reset has no effect on the t8 bit. m ? character length bit this read/write bit determines whether sci characters are 8 bits long or 9 bits long. the ninth bit can be used as an extra stop bit, as a receiver wakeup signal, or as a mark or space parity bit. reset has no effect on the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake ? wakeup bit this read/write bit determines which condition wakes up the sci: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition of the pd0/rdi pin. reset has no effect on the wake bit. 1 = address mark wakeup 0 = idle line wakeup address: $000e bit 7654321bit 0 read: r8 t8 0 m wake 0 0 0 write: reset: unaffected by reset = unimplemented figure 9-5. sci control register 1 (sccr1)
serial communications interface (sci) technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 80 serial communications interface (sci) motorola 9.6.3 sci control register 2 sci control register 2 has these functions: enables the sci receiver and sci receiver interrupts enables the sci transmitter and sci transmitter interrupts enables sci receiver idle interrupts enables sci transmission complete interrupts enables sci wakeup transmits sci break characters tie ? transmit interrupt enable bit this read/write bit enables sci interrupt requests when the tdre bit becomes set. reset clears the tie bit. 1 = tdre interrupt requests enabled 0 = tdre interrupt requests disabled tcie ? transmission complete interrupt enable bit this read/write bit enables sci interrupt requests when the tc bit becomes set. reset clears the tcie bit 1 = tc interrupt requests enabled 0 = tc interrupt requests disabled rie ? receive interrupt enable bit this read/write bit enables sci interrupt requests when the rdrf bit or the or bit becomes set. reset clears the rie bit. 1 = rdrf interrupt requests enabled 0 = rdrf interrupt requests disabled address: $000f bit 7654321bit 0 read: tie tcie rie ilie te re rwu sbk write: reset:00000000 figure 9-6. sci control register 2 (sccr2)
serial communications interface (sci) sci input/output (i/o) registers MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola serial communications interface (sci) 81 ilie ? idle line interrupt enable bit this read/write bit enables sci interrupt requests when the idle bit becomes set. reset clears the ilie bit. 1 = idle interrupt requests enabled 0 = idle interrupt requests disabled te ? transmit enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the pd1/tdo pin. reset clears the te bit. 1 = transmission enabled 0 = transmission disabled re ? receive enable bit setting this read/write bit enables the receiver. clearing the re bit disables the receiver and receiver interrupts but does not affect the receiver interrupt flags. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled rwu ? receiver wakeup enable bit this read/write bit puts the receiver in a standby state. typically, data transmitted to the receiver clears the rwu bit and returns the receiver to normal operation. the wake bit in sccr1 determines whether an idle input or an address mark brings the receiver out of the standby state. reset clears the rwu bit. 1 = standby state 0 = normal operation sbk ? send break bit setting this read/write bit continuously transmits break codes in the form of 10-bit or 11-bit groups of logic 0s. clearing the sbk bit stops the break codes and transmits a logic 1 as a start bit. reset clears the sbk bit. 1 = break codes being transmitted 0 = no break codes being transmitted
serial communications interface (sci) technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 82 serial communications interface (sci) motorola 9.6.4 sci status register the sci status register contains flags to signal these conditions: transfer of scdr data to transmit shift register complete transmission complete transfer of receive shift register data to scdr complete receiver input idle receiver overrun noisy data framing error tdre ? transmit data register empty bit this clearable, read-only bit is set when the data in the scdr transfers to the transmit shift register. tdre generates an interrupt request if the tie bit in sccr2 is also set. clear the tdre bit by reading the scsr with tdre set, and then writing to the scdr. reset sets the tdre bit. software must initialize the tdre bit to logic 0 to avoid an instant interrupt request when turning on the transmitter. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register tc ? transmission complete bit this clearable, read-only bit is set when the tdre bit is set, and no data, preamble, or break character is being transmitted. tc generates an interrupt request if the tcie bit in sccr2 is also set. clear the tc bit by reading the scsr with tc set, and then writing to the scdr. address: $0010 bit 7654321bit 0 read: tdre tc rdrf idle or nf fe 0 write: reset:00000000 = unimplemented figure 9-7. sci status register (scsr)
serial communications interface (sci) sci input/output (i/o) registers MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola serial communications interface (sci) 83 reset sets the tc bit. software must initialize the tc bit to logic 0 to avoid an instant interrupt request when turning on the transmitter. 1 = no transmission in progress 0 = transmission in progress rdrf ? receive data register full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. rdrf generates an interrupt request if the rie bit in sccr2 is also set. clear the rdrf bit by reading the scsr with rdrf set, and then reading the scdr. reset clears the rdrf bit. 1 = received data available in scdr 0 = received data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. idle generates an interrupt request if the ilie bit in sccr2 is also set. clear the idle bit by reading the scsr with idle set, and then reading the scdr. reset clears the idle bit. 1 = receiver input idle 0 = receiver input not idle or ? receiver overrun bit this clearable, read-only bit is set if the scdr is not read before the receive shift register receives the next word. or generates an interrupt request if the rie bit in sccr2 is also set. the data in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading the scsr with or set and then reading the scdr. reset clears the or bit. 1 = receiver shift register full and rdrf = 1 0 = no receiver overrun nf ? receiver noise flag this clearable, read-only bit is set when noise is detected in data received in the sci data register. clear the nf bit by reading the scsr and then reading the scdr. reset clears the nf bit. 1 = noise detected in scdr 0 = no noise detected in scdr
serial communications interface (sci) technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 84 serial communications interface (sci) motorola fe ? receiver framing error flag this clearable, read-only flag is set when there is a logic 0 where a stop bit should be in the character shifted into the receive shift register. if the received word causes both a framing error and an overrun error, the or bit is set and the fe bit is not set. clear the fe bit by reading the scsr, and then reading the scdr. reset clears the fe bit. 1 = framing error 0 = no framing error 9.6.5 baud rate register the baud rate register (baud) selects the baud rate for both the receiver and the transmitter. scp1 and scp0 ? sci prescaler select bits these read/write bits control prescaling of the baud rate generator clock, as shown in table 9-1 . resets clear both scp1 and scp0. address: $000d bit 7654321bit 0 read: 0 0 scp1 scp0 0 scr2 scr2 scr0 write: reset:00000uuu u = unaffected figure 9-8. baud rate register (baud) table 9-1. baud rate generator clock prescaling scp0 ? scp1 baud rate generator clock 00 internal clock divided by 1 01 internal clock divided by 3 10 internal clock divided by 4 11 internal clock divided by 13
serial communications interface (sci) sci input/output (i/o) registers MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola serial communications interface (sci) 85 scr2 ? scr0 ? sci baud rate select bits these read/write bits select the sci baud rate, as shown in table 9-2 . reset has no effect on the scr2 ? scr0 bits. table 9-3 shows all possible sci baud rates derived from crystal frequencies of 2 mhz, 4 mhz, and 4.194304 mhz. table 9-2. baud rate selection scr2 ? scr0 sci baud rate (baud) 000 prescaled clock divided by 1 001 prescaled clock divided by 2 010 prescaled clock divided by 4 011 prescaled clock divided by 8 100 prescaled clock divided by 16 101 prescaled clock divided by 32 110 prescaled clock divided by 64 111 prescaled clock divided by 128
serial communications interface (sci) technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 86 serial communications interface (sci) motorola table 9-3. baud rate selection examples scp[1:0] scr [2:1:0] sci baud rate f osc = 2 mhz f osc = 4 mhz f osc = 4.194304 mhz 00 000 62.50 kbaud 125 kbaud 131.1 kbaud 00 001 31.25 kbaud 62.50 kbaud 65.54 kbaud 00 010 15.63 kbaud 31.25 kbaud 32.77 kbaud 00 011 7813 baud 15.63 kbaud 16.38 kbaud 00 100 3906 baud 7813 baud 8192 baud 00 101 1953 baud 3906 baud 4096 baud 00 110 976.6 baud 1953 baud 2048 baud 00 111 488.3 baud 976.6 baud 1024 baud 01 000 20.83 kbaud 41.67 kbaud 43.69 kbaud 01 001 10.42 kbaud 20.83 kbaud 21.85 kbaud 01 010 5208 baud 10.42 kbaud 10.92 kbaud 01 011 2604 baud 5208 baud 5461 baud 01 100 1302 baud 2604 baud 2731 baud 01 101 651.0 baud 1302 baud 1365 baud 01 110 325.5 baud 651.0 baud 682.7 baud 01 111 162.8 baud 325.5 baud 341.3 baud 10 000 15.63 kbaud 31.25 kbaud 32.77 kbaud 10 001 7813 baud 15.63 kbaud 16.38 kbaud 10 010 3906 baud 7813 baud 8192 baud 10 011 1953 baud 3906 baud 4906 baud 10 100 976.6 baud 1953 baud 2048 baud 10 101 488.3 baud 976.6 baud 1024 baud 10 110 244.1 baud 488.3 baud 512.0 baud 10 111 122.1 baud 244.1 baud 256.0 baud 11 000 4808 baud 9615 baud 10.08 kbaud 11 001 2404 baud 4808 baud 5041 baud 11 010 1202 baud 2404 baud 2521 baud 11 011 601.0 baud 1202 baud 1260 baud 11 100 300.5 baud 601.0 baud 630.2 baud 11 101 150.2 baud 300.5 baud 315.1 baud 11 110 75.12 baud 150.2 baud 157.5 baud 11 111 37.56 baud 75.12 baud 78.77 baud
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola serial peripheral interface (spi) 87 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a a mc68hcl05c8a mc68hsc05c8a section 10. serial peripheral interface (spi) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.4 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 10.4.1 master in slave out (miso) . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.4.2 master out slave in (mosi) . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.4.3 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.4.4 slave select (ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 10.6 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 10.6.1 serial peripheral control register . . . . . . . . . . . . . . . . . . . . 93 10.6.2 serial peripheral status register . . . . . . . . . . . . . . . . . . . . .94 10.6.3 serial peripheral data i/o register . . . . . . . . . . . . . . . . . . . 96 10.2 introduction the serial peripheral interface (spi) is an interface built into the mc68hc05 microcontroller unit (mcu) which allows several mc68hc05 mcus or mc68hc05 mcu plus peripheral devices to be interconnected within a single printed circuit board. in an spi, separate wires are required for data and clock. in the spi format, the clock is not included in the data stream and must be furnished as a separate signal. an spi system may be configured in a system containing one master mcu and several slave mcus or in a system in which an mcu is capable of being a master or a slave.
serial peripheral interface (spi) technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 88 serial peripheral interface (spi) motorola 10.3 features full duplex, 4-wire synchronous transfers master or slave operation bus frequency divided by 2 (maximum) master bit frequency bus frequency (maximum) slave bit frequency four programmable master bit rates programmable clock polarity and phase end-of-transmission interrupt flag write collision flag protection master-master mode fault protection capability 10.4 spi signal description gnal description the four basic signals (mosi, miso, sck, and ss ) are described in this subsection. each signal function is described for both the master and slave mode. 10.4.1 master in slave out (miso) the miso line is configured as an input in a master device and as an output in a slave device. it is one of the two lines that transfer serial data in one direction, with the most significant bit sent first. the miso line of a slave device is placed in the high-impedance state if the slave is not selected. 10.4.2 master out slave in (mosi) the mosi line is configured as an output in a master device and as an input in a slave device. it is one of the two lines that transfer serial data in one direction with the most significant bit sent first.
serial peripheral interface (spi) spi signal description MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola serial peripheral interface (spi) 89 10.4.3 serial clock (sck) the master clock is used to synchronize data movement both in and out of the device through its mosi and miso lines. the master and slave devices are capable of exchanging a byte of information during a sequence of eight clock cycles. since sck is generated by the master device, this line becomes an input on a slave device. as shown in figure 10-1 , four possible timing relationships may be chosen by using control bits cpol and cpha in the serial peripheral control register (spcr). both master and slave devices must operate with the same timing. the master device always places data on the mosi line one-half cycle before the clock edge (sck), so the slave device can latch the data. two bits (spr0 and spr1) in the spcr of the master device select the clock rate. in a slave device, spr0 and spr1 have no effect on the spi operation. figure 10-1. data clock timing diagram internal strobe for data capture (all modes) msb6543210 ss sck sck sck sck miso/mosi
serial peripheral interface (spi) technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 90 serial peripheral interface (spi) motorola 10.4.4 slave select (ss ) the slave select (ss ) input line is used to select a slave device. it has to be low prior to data transactions and must stay low for the duration of the transaction. the ss line on the master must be tied high. if it goes low, a mode fault error flag (modf) is set in the spsr. when cpha = 0, the shift clock is the or of ss with sck. in this clock phase mode, ss must go high between successive characters in an spi message. when cpha = 1, ss may be left low for several spi characters. in cases where there is only one spi slave mcu, its ss line could be tied to v ss as long as cpha = 1 clock modes are used. 10.5 functional description figure 10-2 shows a block diagram of the spi circuitry. when a master device transmits data to a slave via the mosi line, the slave device responds by sending data to the master device via the master ? s miso line. this implies full duplex transmission with both data out and data in synchronized with the same clock signal. thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receive-full status bits. a single status bit (spif) is used to signify that the input/output (i/o) operation has been completed. the spi data register (spdr) is double buffered on read, but not on write. if a write is performed during data transfer, the transfer occurs uninterrupted, and the write will be unsuccessful. this condition will cause the write collision (wcol) status bit in the spsr to be set. after a data byte is shifted, the spif flag of the spsr is set. in the master mode, the sck pin is an output. it idles high or low, depending on the cpol bit in the spcr, until data is written to the shift register, at which point eight clocks are generated to shift the eight bits of data and then sck goes idle again.
serial peripheral interface (spi) functional description MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola serial peripheral interface (spi) 91 figure 10-2. serial peripheral interface block diagram divider 2 4 16 32 select 8-bit shift reg read data buff msb lsb s m m s s m pin control logic clock clock logic spi clock mstr spe spie spe mstr cpha cpol spr1 spr0 spi control register internal data bus spi interrupt request spi status register spr1 spr0 spi control spif wcol modf internal mcu clock sck pd4 ss pd5 mosi pd3 miso pd2 (master)
serial peripheral interface (spi) technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 92 serial peripheral interface (spi) motorola in a slave mode, the slave select start logic receives a logic low at the ss pin and a clock at the sck pin. thus, the slave is synchronized with the master. data from the master is received serially at the mosi line and loads the 8-bit shift register. after the 8-bit shift register is loaded, its data is parallel transferred to the read buffer. during a write cycle, data is written into the shift register, then the slave waits for a clock train from the master to shift the data out on the slave ? s miso line. figure 10-3 illustrates the mosi, miso, sck, and ss master-slave interconnections. figure 10-3. serial peripheral interface master-slave interconnection 10.6 spi registers this subsection describes the three registers in the spi which provide control, status, and data storage functions. these registers are: serial peripheral control register (spcr) serial peripheral status register (spsr) serial peripheral data i/o register (spdr) i/o port spdr ($000c) spdr ($000c) spi shift register spi shift register pd3/mosi pd2/miso pd4/sck master mcu slave mcu ss pd5
serial peripheral interface (spi) spi registers MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola serial peripheral interface (spi) 93 10.6.1 serial peripheral control register spie ? serial peripheral interrupt enable bit 0 = spif interrupts disabled 1 = spi interrupt is enabled spe ? serial peripheral system enable bit 0 = spi system off 1 = spi system on mstr ? master mode select bit 0 = slave mode 1 = master mode cpol ? clock polarity bit when the clock polarity bit is cleared and data is not being transferred, a steady state low value is produced at the sck pin of the master device. conversely, if this bit is set, the sck pin will idle high. this bit also is used in conjunction with the clock phase control bit to produce the desired clock-data relationship between master and slave. see figure 10-1 . cpha ? clock phase bit the clock phase bit, in conjunction with the cpol bit, controls the clock-data relationship between master and slave. the cpol bit can be thought of as simply inserting an inverter in series with the sck line. the cpha bit selects one of two fundamentally different clocking protocols. when cpha = 0, the shift clock is the or of sck with ss . address: $000a bit 7654321bit 0 read: spie spe mstr cpol cpha spr1 spr0 write: reset000000uu = unimplemented u = unaffected figure 10-4. spi control register (spcr)
serial peripheral interface (spi) technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 94 serial peripheral interface (spi) motorola as soon as ss goes low, the transaction begins and the first edge on sck invokes the first data sample. when cpha = 1, the ss pin may be thought of as a simple output enable control. see figure 10-1 . spr1 and spr0 ? spi clock rate select bits these two bits select one of four baud rates to be used as sck if the device is a master; however, they have no effect in the slave mode. see table 10-1. 10.6.2 serial peripheral status register spif ? spi transfer complete flag the serial peripheral data transfer flag bit is set upon completion of data transfer between the processor and external device. if spif goes high and if spie is set, a serial peripheral interrupt is generated. clearing the spif bit is accomplished by reading the spsr (with spif set) followed by an access of the spdr. unless spsr is read (with spif set) first, attempts to write to spdr are inhibited. table 10-1. serial peripheral rate selection spr1 spr0 bus clock divided by 00 2 01 4 10 16 11 32 address: $000b bit 7654321bit 0 read: spif wcol 0 modf 0000 write: reset000000uu = unimplemented u = unaffected figure 10-5. spi status register (spsr)
serial peripheral interface (spi) spi registers MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola serial peripheral interface (spi) 95 wcol ? write collision bit the write collision bit is set when an attempt is made to write to the serial peripheral data register while data transfer is taking place. if cpha is 0, a transfer is said to begin when ss goes low and the transfer ends when ss goes high after eight clock cycles on sck. when cpha is 1, a transfer is said to begin the first time sck becomes active while ss is low. the transfer ends when the spif flag gets set. clearing the wcol bit is accomplished by reading the spsr (with wcol set) followed by an access to spdr. bit 5 ? not implemented this bit always reads as 0. modf ? mode fault flag the mode fault flag indicates that there may have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state. the modf bit is normally clear and is set only when the master device has its ss pin pulled low. setting the modf bit affects the internal serial peripheral interface system in these ways: an spi interrupt is generated if spie = 1. the spe bit is cleared. this disables the spi. the mstr bit is cleared, thus forcing the device into the slave mode. clearing the modf bit is accomplished by reading the spsr (with modf set), followed by a write to the spcr. control bits spe and mstr may be restored by user software to their original state after the modf bit has been cleared. bits 3 ? 0 ? not implemented these bits always reads as 0.
serial peripheral interface (spi) technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 96 serial peripheral interface (spi) motorola 10.6.3 serial peripheral data i/o register the serial peripheral data i/o register is used to transmit and receive data on the serial bus. only a write to this register will initiate transmission/reception of another byte, and this will occur only in the master device. at the completion of transmitting a byte of data, the spif status bit is set in both the master and slave devices. when the user reads the serial peripheral data i/o register, a buffer is actually being read. the first spif must be cleared by the time a second transfer of the data from the shift register to the read buffer is initiated or an overrun condition will exist. in cases of overrun, the byte which causes the overrun is lost. a write to the serial peripheral data i/o register is not buffered and places data directly into the shift register for transmission. address: $000c bit 7654321bit 0 read: spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 write: reset unaffected by reset figure 10-6. spi data register (spsr)
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola operating modes 97 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a l05c8a mc68hsc05c8a section 11. operating modes 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.3 user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.4 self-check mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.4.1 self-check tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.4.2 self-check results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.2 introduction the microcontroller unit (mcu) has two modes of operation: user mode and self-check mode. table 11-1 shows the conditions required to enter into each mode, where v tst = 2 x v dd . table 11-1. operating mode conditions reset irq tcap mode v ss to v dd v ss to v dd user v tst v dd self-check
operating modes technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 98 operating modes motorola 11.3 user mode in user mode, the address and data buses are not available externally, but there are three 8-bit input/output (i/o) ports and one 7-bit input-only port. this mode allows the mcu to function as a self-contained microcontroller, with maximum use of the pins for on-chip peripheral functions. all address and data activity occurs within the mcu. user mode is entered on the rising edge of reset if the irq pin is within normal operating range. figure 11-1. user mode pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 28 29 30 31 32 33 34 35 36 37 38 39 40 v dd osc1 osc2 tcap pd7 pd6/tcmp pd5/ss pd4/sck pd3/mosi pd2/miso pd1/tdo pd0/rdi pc0 pc1 reset irq nc pa7 pa5 pa4 pa3 pa2 pa1 pa0 pb0 pb1 pb2 pa6 15 16 17 18 19 20 pb4 pb5 pb6 pb7 v ss pb3 21 22 23 24 25 26 pc2 pc3 pc4 pc5 pc6 pc7
operating modes self-check mode MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola operating modes 99 11.4 self-check mode k mode self-check mode is entered upon the rising edge of reset if the irq pin is at v tst and the tcap pin is at logic 1. 11.4.1 self-check tests the self-check read-only memory (rom) at mask rom location $1f00 ? $1fef determines if the mcu is functioning properly.these tests are performed: 1. i/o ? functional test of ports a, b, and c 2. random-access memory (ram) ? counter test for each ram byte 3. timer ? test of counter register and ocf bit 4. serial communications interface (sci) ? transmission test checks for rdrf, tdre, tc, and fe flags 5. read-only memory (rom) ? exclusive or with odd ones parity result 6. serial peripheral interface (spi) ? transmission test checks for spif and wcol flags the self-check circuit is shown in figure 11-2 .
operating modes technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 100 operating modes motorola 11.4.2 self-check results table 11-2 shows the light-emitting diode (led) codes that indicate self- check test results. perform these steps to activate the self-check tests: 1. apply 10 v (2 x v dd ) to the irq pin. 2. apply a logic 1 to the tcap pin. 3. apply a logic 0 to the reset pin. the self-check tests begin on the rising edge of the reset pin. reset must be held low for 4064 cycles after power-on reset (por) or for a time, t rl , for any other reset. for the t rl value, see 13.9 5.0-v control timing . table 11-2. self-check circuit led codes pc3 pc2 pc1 pc0 remarks off on on off i/o failure off on off on ram failure off on off off timer failure off off on on sci failure off off on off rom failure off off off on spi failure flashing no failure all others device failure
operating modes self-check mode MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola operating modes 101 figure 11-2. self-check circuit schematic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 28 29 30 31 32 33 34 35 36 37 38 39 40 15 16 17 18 19 20 21 22 23 24 25 26 v dd 4.7 k ? reset irq pa5 pa4 pa3 pa2 pa1 pa0 pb0 pa6 pb1 pb2 nc pa7 pb3 pb4 pb5 pb6 pb7 v ss 20 pf 10 m ? 4 mhz 20 pf pc0 v dd osc1 osc2 tcap pd7 tcmp pd5/ss pd4/sck pd3/mosi pd2/miso pd1/tdo pd0/rdi pc1 pc2 pc3 pc4 pc5 pc6 pc7 v dd 1 m ? 10 v mc68h05c8a mc34064 v dd v dd cmos buffer (mc74hc125) 330 ? 330 ? 330 ? 330 ? notes: 2. tcmp = nc v dd 10 k ? 1. v dd = 5.0 v
operating modes technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 102 operating modes motorola
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola instruction set 103 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a section 12. instruction set 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.2 immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.6 indexed, 8-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.7 indexed, 16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.4.1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . 108 12.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . 109 12.4.3 jump/branch instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . .112 12.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 12.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.6 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
instruction set technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 104 instruction set motorola 12.2 introduction the microcontroller unit (mcu) instruction set has 62 instructions and uses eight addressing modes. the instructions include all those of the m146805 cmos (complementary metal oxide silicon) family plus one more: the unsigned multiply (mul) instruction. the mul instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is stored in the index register, and the low-order product is stored in the accumulator. 12.3 addressing modes the central processor unit (cpu) uses eight addressing modes for flexibility in accessing data. the addressing modes provide eight different ways for the cpu to find the data required to execute an instruction. the eight addressing modes are: inherent immediate direct extended indexed, no offset indexed, 8-bit offset indexed, 16-bit offset relative
instruction set addressing modes MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola instruction set 105 12.3.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry flag (sec) and increment accumulator (inca). inherent instructions require no operand address and are one byte long. 12.3.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no operand address and are two bytes long. the opcode is the first byte, and the immediate data value is the second byte. 12.3.3 direct direct instructions can access any of the first 256 memory locations with two bytes. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. 12.3.4 extended extended instructions use three bytes and can access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction.
instruction set technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 106 instruction set motorola 12.3.5 indexed, no offset indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the effective address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000 ? $00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used random-access memory (ram) or input/output (i/o) location. 12.3.6 indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the effective address of the operand. these instructions can access locations $0000 ? $01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 12.3.7 indexed, 16-bit offset indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the effective address of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory.
instruction set instruction types MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola instruction set 107 as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. 12.3.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, two ? s complement byte that gives a branching range of ? 128 to +127 bytes from the address of the next location after the branch instruction. when using the motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. 12.4 instruction types 4 instruction types the mcu instructions fall into the following five categories: register/memory instructions read-modify-write instructions jump/branch instructions bit manipulation instructions control instructions
instruction set technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 108 instruction set motorola 12.4.1 register/memory instructions these instructions operate on cpu registers and memory locations. most of them use two operands. one operand is in either the accumulator or the index register. the cpu finds the other operand in memory. table 12-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub
instruction set instruction types MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola instruction set 109 12.4.2 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. note: do not use read-modify-write operations on write-only registers. table 12-2. read-modify-write instructions instruction mnemonic arithmetic shift left (same as lsl) asl arithmetic shift right asr bit clear bclr (1) 1. unlike other read-modify-write instructions, bclr and bset use only direct addressing. bit set bset (1) clear register clr complement (one ? s complement) com decrement dec increment inc logical shift left (same as asl) lsl logical shift right lsr negate (two ? s complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst (2) 2. tst is an exception to the read-modify-write sequence because it does not write a replacement value.
instruction set technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 110 instruction set motorola 12.4.3 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. the brclr and brset instructions cause a branch based on the state of any readable bit in the first 256 memory locations. these 3-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from ? 128 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register.
instruction set instruction types MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola instruction set 111 table 12-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr
instruction set technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 112 instruction set motorola 12.4.4 bit manipulation instructions the cpu can set or clear any writable bit in the first 256 bytes of memory, which includes i/o registers and on-chip ram locations. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. 12.4.5 control instructions these instructions act on cpu registers and control cpu operation during program execution. table 12-4. bit manipulation instructions instruction mnemonic bit clear bclr branch if bit clear brclr branch if bit set brset bit set bset table 12-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait
instruction set instruction set summary MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola instruction set 113 12.5 instruction set summary table 12-6. instruction set summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a (a) (m) ?? ? imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right ?? dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 bclr n opr clear bit n mn 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? z = 1 ????? rel 27 rr 3 bhcc rel branch if half-carry bit clear pc (pc) + 2 + rel ? h = 0 ????? rel 28 rr 3 bhcs rel branch if half-carry bit set pc (pc) + 2 + rel ? h = 1 ????? rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? c z = 0 ????? rel 22 rr 3 c b0 b7 0 b0 b7 c
instruction set technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 114 instruction set motorola bhs rel branch if higher or same pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ????? rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ????? rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) ?? ? imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? c z = 1 ????? rel 23 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? i = 0 ????? rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? n = 1 ????? rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? i = 1 ????? rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? z = 0 ????? rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? n = 0 ????? rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ? 1 = 1 ????? rel 20 rr 3 brclr n opr rel branch if bit n clear pc (pc) + 2 + rel ? mn = 0 ???? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 + rel ? 1 = 0 ????? rel 21 rr 3 brset n opr rel branch if bit n set pc (pc) + 2 + rel ? mn = 1 ???? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ????? rel ad rr 6 table 12-6. instruction set summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc
instruction set instruction set summary MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola instruction set 115 clc clear carry bit c 0 ???? 0inh98 2 cli clear interrupt mask i 0 ? 0 ??? inh 9a 2 clr opr clra clrx clr opr ,x clr ,x clear byte m $00 a $00 x $00 m $00 m $00 ?? 01 ? dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ? (m) ?? imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (one ? s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (a) x (x ) = $ff ? (x) m (m ) = $ff ? (m) m (m ) = $ff ? (m) ?? 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ? (m) ?? imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a (a) (m) ?? ? imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc jump address ????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 table 12-6. instruction set summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc
instruction set technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 116 instruction set motorola jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n (n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc effective address ????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a (m) ?? ? imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x (m) ?? ? imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) ?? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right ?? 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a (x) (a) 0 ??? 0inh42 1 1 neg opr nega negx neg opr ,x neg ,x negate byte (two ? s complement) m ? (m) = $00 ? (m) a ? (a) = $00 ? (a) x ? (x) = $00 ? (x) m ? (m) = $00 ? (m) m ? (m) = $00 ? (m) ?? dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation ????? inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a (a) (m) ?? ? imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit ?? dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 table 12-6. instruction set summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0 c b0 b7
instruction set instruction set summary MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola instruction set 117 ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit ?? dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp $00ff ????? inh 9c 2 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ????? inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c 1 ???? 1inh99 2 sei set interrupt mask i 1 ? 1 ??? inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m (a) ?? ? dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin ? 0 ??? inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m (x) ?? ? dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a (a) ? (m) ?? imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ? 1 ??? inh 83 1 0 table 12-6. instruction set summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc b0 b7 c
instruction set technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 118 instruction set motorola 12.6 opcode map see table 12-7 . tax transfer accumulator to index register x (a) ????? inh 97 2 tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ? $00 ?? ? dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a (x) ????? inh 9f 2 wait stop cpu clock and enable interrupts ? 0 ??? inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ? ( ) negation (two ? s complement) ix1 indexed, 8-bit offset addressing mode loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative flag set or cleared n any bit ? not affected table 12-6. instruction set summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola instruction set 119 instruction set opcode map table 12-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789abcdef 0 5 brset0 3dir 5 bset0 2dir 3 bra 2rel 5 neg 2dir 3 nega 1inh 3 negx 1inh 6 neg 2ix1 5 neg 1ix 9 rti 1inh 2 sub 2imm 3 sub 2dir 4 sub 3 ext 5 sub 3ix2 4 sub 2ix1 3 sub 1ix 0 1 5 brclr0 3dir 5 bclr0 2dir 3 brn 2rel 6 rts 1inh 2 cmp 2imm 3 cmp 2dir 4 cmp 3 ext 5 cmp 3ix2 4 cmp 2ix1 3 cmp 1ix 1 2 5 brset1 3dir 5 bset1 2dir 3 bhi 2rel 11 mul 1inh 2 sbc 2imm 3 sbc 2dir 4 sbc 3 ext 5 sbc 3ix2 4 sbc 2ix1 3 sbc 1ix 2 3 5 brclr1 3dir 5 bclr1 2dir 3 bls 2rel 5 com 2dir 3 coma 1inh 3 comx 1inh 6 com 2ix1 5 com 1ix 10 swi 1inh 2 cpx 2imm 3 cpx 2dir 4 cpx 3 ext 5 cpx 3ix2 4 cpx 2ix1 3 cpx 1ix 3 4 5 brset2 3dir 5 bset2 2dir 3 bcc 2rel 5 lsr 2dir 3 lsra 1inh 3 lsrx 1inh 6 lsr 2ix1 5 lsr 1ix 2 and 2imm 3 and 2dir 4 and 3 ext 5 and 3ix2 4 and 2ix1 3 and 1ix 4 5 5 brclr2 3dir 5 bclr2 2dir 3 bcs/blo 2rel 2 bit 2imm 3 bit 2dir 4 bit 3 ext 5 bit 3ix2 4 bit 2ix1 3 bit 1ix 5 6 5 brset3 3dir 5 bset3 2dir 3 bne 2rel 5 ror 2dir 3 rora 1inh 3 rorx 1inh 6 ror 2ix1 5 ror 1ix 2 lda 2imm 3 lda 2dir 4 lda 3 ext 5 lda 3ix2 4 lda 2ix1 3 lda 1ix 6 7 5 brclr3 3dir 5 bclr3 2dir 3 beq 2rel 5 asr 2dir 3 asra 1inh 3 asrx 1inh 6 asr 2ix1 5 asr 1ix 2 ta x 1inh 4 sta 2dir 5 sta 3 ext 6 sta 3ix2 5 sta 2ix1 4 sta 1ix 7 8 5 brset4 3dir 5 bset4 2dir 3 bhcc 2rel 5 asl/lsl 2dir 3 asla/lsla 1inh 3 aslx/lslx 1inh 6 asl/lsl 2ix1 5 asl/lsl 1ix 2 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3 ext 5 eor 3ix2 4 eor 2ix1 3 eor 1ix 8 9 5 brclr4 3dir 5 bclr4 2dir 3 bhcs 2rel 5 rol 2dir 3 rola 1inh 3 rolx 1inh 6 rol 2ix1 5 rol 1ix 2 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3 ext 5 adc 3ix2 4 adc 2ix1 3 adc 1ix 9 a 5 brset5 3dir 5 bset5 2dir 3 bpl 2rel 5 dec 2dir 3 deca 1inh 3 decx 1inh 6 dec 2ix1 5 dec 1ix 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3 ext 5 ora 3ix2 4 ora 2ix1 3 ora 1ix a b 5 brclr5 3dir 5 bclr5 2dir 3 bmi 2rel 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3 ext 5 add 3ix2 4 add 2ix1 3 add 1ix b c 5 brset6 3dir 5 bset6 2dir 3 bmc 2rel 5 inc 2dir 3 inca 1inh 3 incx 1inh 6 inc 2ix1 5 inc 1ix 2 rsp 1inh 2 jmp 2dir 3 jmp 3 ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix c d 5 brclr6 3dir 5 bclr6 2dir 3 bms 2rel 4 tst 2dir 3 tsta 1inh 3 tstx 1inh 5 tst 2ix1 4 tst 1ix 2 nop 1inh 6 bsr 2rel 5 jsr 2dir 6 jsr 3 ext 7 jsr 3ix2 6 jsr 2ix1 5 jsr 1ix d e 5 brset7 3dir 5 bset7 2dir 3 bil 2rel 2 stop 1inh 2 ldx 2imm 3 ldx 2dir 4 ldx 3 ext 5 ldx 3ix2 4 ldx 2ix1 3 ldx 1ix e f 5 brclr7 3dir 5 bclr7 2dir 3 bih 2rel 5 clr 2dir 3 clra 1inh 3 clrx 1inh 6 clr 2ix1 5 clr 1ix 2 wait 1inh 2 txa 1inh 4 stx 2dir 5 stx 3 ext 6 stx 3ix2 5 stx 2ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb
instruction set technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 120 instruction set motorola
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola electrical specifications 121 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a section 13. electrical specifications 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 13.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 13.4 operating temperature range. . . . . . . . . . . . . . . . . . . . . . . . 122 13.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.6 power considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.7 5.0-v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . 125 13.8 3.3-v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . 126 13.9 5.0-v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.10 3.3-v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 13.11 5.0-v serial peripheral interface timing . . . . . . . . . . . . . . . 132 13.12 3.3-v serial peripheral interface timing . . . . . . . . . . . . . . . 133 13.2 introduction this section contains the electrical and timing specifications.
electrical specifications technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 122 electrical specifications motorola 13.3 maximum ratings mum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. the mcu contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . note: this device is not guaranteed to operate properly at the maximum ratings. refer to 13.7 5.0-v dc electrical characteristics and 13.8 3.3-v dc electrical characteristics for guaranteed operating conditions. 13.4 operating temperature range rating symbol value unit supply voltage v dd ? 0.3 to +7.0 v current drain per pin excluding v dd and v ss i25ma irq pin only v in v ss ? 0.3 to 2 x v dd + 0.3 v storage temperature range t stg ? 65 to +150 c characteristic symbol value unit operating temperature range (1) MC68HC05C8Ap, fn, b, fb mc68hsc05c8cp, cfn, cb, cfb MC68HC05C8Avp, vn, vb, vfb MC68HC05C8Amp, mfn, mb, mfb 1. p = plastic dual in-line package (pdip) fn = plastic-leaded chip carrier (plcc) b = shrink dual in-line-package (sdip) fb = quad flat pack (qfp) t a t l to t h 0 to +70 ? 40 to +85 ? 40 to +105 ? 40 to +125 c
electrical specifications thermal characteristics MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola electrical specifications 123 13.5 thermal characteristics 13.6 power considerations the average chip-junction temperature, t j , in c, can be obtained from: t j = t a + (p d ja )(1) where: t a = ambient temperature, c ja = package thermal resistance, junction to ambient, c/w. p d = p int + p i/o p int = i dd v dd watts (chip internal power) p i/o = power dissipation on input and output pins (user-determined) for most applications p i/o ? p int and can be neglected. following is an approximate relationship between p d and t j (neglecting p i/o ): p d = k (t j + 273 c) (2) solving equations (1) and (2) for k gives: k = p d (t a + 273 c) + ja (p d ) 2 (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . characteristic symbol value unit thermal resistance plastic dual in-line package plastic leaded chip carrier (plcc) quad flat pack (qfp0) plastic shrink dip (sdip) ja 60 70 95 60 c/w
electrical specifications technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 124 electrical specifications motorola figure 13-1. test load v dd = 3.0 v pins r1 r2 c pa 7 ? pa 0 pb7 ? pb0 pc7 ? pc0 pd5 ? pd0, pd7 10.91 ? 6.32 ? 50 pf v dd = 4.5 v pins r1 r2 c pa 7 ? pa 0 pb7 ? pb0 pc7 ? pc0 pd5 ? pd0, pd7 3.26 ? 2.38 ? 50 pf v dd c r2 r1 test point see see table see table table
electrical specifications 5.0-v dc electrical characteristics MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola electrical specifications 125 13.7 5.0-v dc electrical characteristics dc electrical characteristics characteristic (1) symbol min typ (2) max unit output voltage i load = 10.0 a i load = ? 10.0 a v ol v oh ? v dd ? 0.1 ? ? 0.1 ? v output high voltage (i load = ? 0.8 ma) pa7 ? pa 0 , p b 7 ? pb0, pc6 ? pc0, tcmp (i load = ? 1.6 ma) pd4 ? pd1 (i load = ? 5.0 ma) pc7 v oh v dd ? 0.8 v dd ? 0.8 v dd ? 0.8 ? ? ? ? ? ? v output low voltage (i load = 1.6 ma) pa7 ? pa0, pb7 ? pb0, pc6 ? pc0, pd4 ? pd1, tcmp (i load = 10 ma) pc7 v ol ? ? ? ? 0.4 0.4 v input high voltage pa 7 ? pa0, pb7 ? pb0, pc7 ? pc0, pd7, pd5 ? pd0, tcap, irq , reset , osc1 v ih 0.7 v dd ? v dd v input low voltage pa 7 ? pa0, pb7 ? pb0, pc7 ? pc0, pd7, pd5 ? pd0, tcap, irq , reset , osc1 v il v ss ? 0.2 v dd v supply current (4.5 ? 5.5 vdc @ f bus = 2.1 mhz) run (3) wait (4) stop (5) 25 c 0 c to 70 c (standard) ? 40 c to +125 c (standard) i dd ? ? ? ? ? 3.50 1.00 1 ? ? 5.25 3.25 20 40 50 ma ma a a a i/o ports hi-z leakage current pa 7 ? pa0, pb7 ? pb0 (without pullup) pc7 ? pc0, pd7, pd5 ? pd0 i oz ?? 10 a input current reset , irq , osc1, tcap, pd7, pd5 ? pd0 i in ?? 1 a input pullup current (6) pb7 ? pb0 (with pullup) i in 175 385 750 a capacitance ports (as input or output) reset , irq , osc1, tcap, pd7, pd5, pd0 c out c in ? ? ? ? 12 8 pf 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ? 40 c to +125 c, unless otherwise noted. 2. typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source; all i/o pins configured as inputs, port b = v dd , all other inputs v il = 0.2 v, v ih = v dd ? 0.2 v; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2. 4. wait i dd measured using external square wave clock source; all i/o pins configured as inputs, port b = v dd , all other inputs v il = 0.2 v, v ih = v dd ? 0.2 v; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2. wait i dd is affected linearly by the osc2 capacitance. 5. stop i dd measured with osc1 = 0.2 v; all i/o pins configured as inputs, port b = v dd , all other inputs v il = 0.2 v, v ih = v dd ? 0.2 v. 6. input pullup current measured with v il = 0.2 v.
electrical specifications technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 126 electrical specifications motorola 13.8 3.3-v dc electrical characteristics characteristic (1) 1. v dd = 3.3 vdc 0.3 vdc, v ss = 0 vdc, t a = ? 40 c to +125 c, unless otherwise noted. symbol min typ (2) 2. typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 c only. max unit output voltage i load = 10.0 a i load = ? 10.0 a v ol v oh ? v dd ? 0.1 ? ? 0.1 ? v output high voltage (i load = ? 0.2 ma) pa7 ? pa 0 , p b 7 ? pb0, pc6 ? pc0, tcmp (i load = ? 0.4 ma) pd4 ? pd1 (i load = ? 1.5 ma) pc7 v oh v dd ? 0.3 v dd ? 0.3 v dd ? 0.3 ? ? ? ? ? ? v output low voltage (i load = 0.4 ma) pa7 ? pa0, pb7 ? pb0, pc6 ? pc0, pd4 ? pd1, tcmp (i load = 6 ma) pc7 v ol ? ? ? ? 0.3 0.3 v input high voltage pa 7 ? pa0, pb7 ? pb0, pc7 ? pc0, pd7, pd5 ? pd0, tcap, irq , reset , osc1 v ih 0.7 v dd ? v dd v input low voltage pa 7 ? pa0, pb7 ? pb0, pc7 ? pc0, pd7, pd5 ? pd0, tcap, irq , reset , osc1 v il v ss ? 0.2 v dd v supply current (3.0 ? 3.6 vdc @ f bus = 1.0 mhz) run (3) wait (4) stop (5) 25 c 0 c to +70 c (standard) ? 40 c to +125 c (standard) 3. run (operating) i dd measured using external square wave clock source; all i/o pins configured as inputs, port b = v dd , all other inputs v il = 0.2 v, v ih = v dd ? 0.2 v; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2. 4. wait i dd measured using external square wave clock source; all i/o pins configured as inputs, port b = v dd , all other inputs v il = 0.2 v, v ih = v dd ? 0.2 v; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2. wait i dd is affected linearly by the osc2 capacitance. 5. stop i dd measured with osc1 = 0.2 v; all i/o pins configured as inputs, port b = v dd , all other inputs v il = 0.2 v, v ih = v dd ? 0.2 v. i dd ? ? ? ? ? 1.00 500 1 ? ? 1.60 900 8 16 20 ma a a a a i/o ports hi-z leakage current pa 7 ? pa0, pb7 ? pb0 (without pullup) pc7 ? pc0, pd7, pd5 ? pd0 i oz ?? 10 a input current reset , irq , osc1, tcap, pd7, pd5, pd0 i in ?? 1 a input pullup current (6) pb7 ? pb0 (with pullup) 6. input pullup current measured with v il = 0.2 v. i in 75 175 350 a capacitance ports (as input or output) reset , irq , osc1, tcap, pd7, pd5, pd0 c out c in ? ? ? ? 12 8 pf
electrical specifications 3.3-v dc electrical characteristics MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola electrical specifications 127 figure 13-2. maximum supply current versus internal clock frequency, v dd = 5.5 v figure 13-3. maximum supply current versus internal clock frequency, v dd = 3.6 v 1.00 ma 2.00 ma 3.00 ma 4.00 ma 5.00 ma 1.5 mhz 2.0 mhz 0.5 mhz 1.0 mhz internal clock frequency (xtal 2) supply current (i dd ) 50 a stop i dd w a it i d d r u n ( o p e r a t i n g ) i d d (mhz) v dd = 5.5 v t = ? 40 c to 125 c 500 ma 1.00 ma 1.50 ma 0.5 mhz 1.0 mhz internal clock frequency (xtal 2) supply current (i dd ) w a i t i d d r u n ( op e r a t i n g) i d d v dd = 3.6 v t = ? 40 c to 125 c stop i dd
electrical specifications technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 128 electrical specifications motorola 13.9 5.0-v control timing characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ? 40 c to +125 c, unless otherwise noted. symbol min max unit oscillator frequency crystal external clock f osc ? dc 4.2 4.2 mhz internal operating frequency crystal external clock f op ? dc 2.1 2.1 mhz internal clock cycle time t cyc 480 ? ns crystal oscillator startup time t oxov ? 100 ms stop recovery startup time (crystal oscillator) t ilch ? 100 ms reset pulse width t rl 1.5 ? t cyc timer resolution (2) input capture pulse width input capture pulse period 2. because a 2-bit prescaler in the timer must count four internal cycles (t cyc ), this is the limiting minimum factor in determining the timer resolution. t resl t th , t tl t tltl 4.0 125 note (3) 3. the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . ? ? ? t cyc ns t cyc interrupt pulse width low (edge-triggered) t ilih 125 ? ns interrupt pulse period t ilil note (4) 4. the minimum t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 t cyc . ? t cyc osc1 pulse width t oh, t ol 90 ? ns
electrical specifications 3.3-v control timing MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola electrical specifications 129 13.10 3.3-v control timing figure 13-4. tcap timing relationships characteristic (1) 1. v dd = 3.3 vdc 0.3 vdc, v ss = 0 vdc, t a = ? 40 c to +125 c, unless otherwise noted. symbol min max unit oscillator frequency crystal external clock f osc ? dc 2.0 2.0 mhz internal operating frequency crystal external clock f op ? dc 1.00 1.00 mhz internal clock cycle time t cyc 1000 ? ns crystal oscillator startup time t oxov 100 ms stop recovery startup time (crystal oscillator) t ilch 100 ms reset pulse width t rl 1.5 ? t cyc timer resolution (2) input capture pulse width input capture pulse period 2. because a 2-bit prescaler in the timer must count four internal cycles (t cyc ), this is the limiting minimum factor in determining the timer resolution. t resl t th , t tl t tltl 4.0 250 note (3) 3. the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . ? ? ? t cyc ns t cyc interrupt pulse width low (edge-triggered) t ilih 250 ? ns interrupt pulse period t ilil note (4) 4. the minimum t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 t cyc . ? t cyc osc1 pulse width t oh, t ol 200 ? ns t tltl tcap pin t th t tl
electrical specifications technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 130 electrical specifications motorola figure 13-5. external interrupt timing figure 13-6. external reset timing normally used with wired-or connection irq t ilih t ilil t ilih irq pin irq 1 irq n . . . a. edge-sensitive trigger condition. the minimum pulse width (t ilih ) is either 125 ns (f op = 2.1 mhz) or 250 ns (f op = 1 mhz). the period t ilil should not be less than the number of t cyc cycles it takes to execute the interrupt service routine plus 19 t cyc cycles. b. level-sensitive trigger condition. if after servicing an interrupt the irq remains low, the next interrupt is recognized. (internal) internal clock (1) internal address bus (1) notes: internal data bus (1) 1ffe 1ffe 1fff new pc 1. internal clock, internal address bus, and internal data bus are not available externally. 2. the next rising edge of the internal clock after the rising edge of reset initiates the reset sequence. new pch t rl new pcl op code reset (2) 1ffe 1ffe
electrical specifications 3.3-v control timing MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola electrical specifications 131 figure 13-7. stop recovery timing diagram figure 13-8. power-on reset timing diagram t ilih 4064 t cyc osc (1) t rl reset irq (2) irq (3) internal clock internal address bus notes: 1. represents the internal clocking of the osc1 pin 2. irq pin edge-sensitive mask option 3. irq pin level- and edge-sensitive mask option 4. reset vector address shown for timing example reset or interrupt vector fetch 1ffe 1ffe 1ffe 1ffe 1ffe 1fff (4) 1ffe 4064 t cyc v dd osc1 pin (2) internal clock (3) internal address bus (3) internal data bus (3) 1ffe 1ffe 1ffe 1ffe 1ffe 1fff (note 1) 1. power-on reset threshold is typically between 1 v and 2 v. 3. internal clock, internal address bus, and internal data bus are not available externally. new pch new pcl 2. osc1 line is meant to represent time only, not frequency. notes:
electrical specifications technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 132 electrical specifications motorola 13.11 5.0-v serial peripheral interface timing num characteristic (1) 1. v dd = 5.0 vdc 10%; v ss = 0 vdc, t a = t l to t h . refer to figure 13-9 and figure 13-10 for timing diagrams. symbol min max unit operating frequency master slave f op(m) f op(s) dc dc 0.5 2.1 f op mhz 1 cycle time master slave t cyc(m) t cyc(s) 2.0 480 ? ? t cyc ns 2 enable lead time master slave t lead(m) t lead( s ) (2) 240 2. signal production depends on software. ? ? ns 3 enable lag time master slave t l ag(m) t l ag(s) (2) 720 ? ? ns 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s 340 190 ? ? ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s 340 190 ? ? ns 6 data setup time (inputs) master slave t su(m) t su(s) 100 100 ? ? ns 7 data hold time (inputs) master slave t h(m) t h(s) 100 100 ? ? ns 8 slave access time (time-to-data active from high- impedance state) t a 0 120 ns 9 slave disable time (hold time to high-impedance state) t dis ? 240 ns 10 data valid master (before capture edge) slave (after enable edge) (3) 3. assumes 200 pf load on all spi pins t v(m) t v(s) 0.25 ? ? 240 t cyc(m) ns 11 data hold time (outputs) master (after capture edge) slave (after enable edge) t ho(m) t ho(s) 0.25 0 ? ? t cyc(m) ns 12 rise time (20% v dd to 70% v dd , c l = 200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t rm t rs ? ? 100 2.0 ns s 13 fall time (70% v dd to 20% v dd , c l = 200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t fm t fs ? ? 100 2.0 ns s
electrical specifications 3.3-v serial peripheral interface timing MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola electrical specifications 133 13.12 3.3-v serial peripheral interface timing num characteristic (1) 1. v dd = 3.3 vdc 0.3 vdc; v ss = 0 vdc, t a = t l to t h . refer to figure 13-9 and figure 13-10 for timing diagrams. symbol min max unit operating frequency master slave f op(m) f op(s) dc dc 0.5 1.0 f op mhz 1 cycle time master slave t cyc(m) t cyc(s) 2.0 1.0 ? ? t cyc s 2 enable lead time master slave t lead(m) t lead(s) (2) 500 2. signal production depends on software. ? ? ns 3 enable lag time master slave t lag(m) t lag(s) (2) 1.5 ? ? ns s 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s 720 400 ? ? ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s 720 400 ? ? ns 6 data setup time (inputs) master slave t su(m) t su(s) 200 200 ? ? ns 7 data hold time (inputs) master slave t h(m) t h(s) 200 200 ? ? ns 8 slave access time (time to data active from high-impedance state) t a 0 250 ns 9 slave disable time (hold time to high-impedance state) t dis ? 500 ns 10 data valid master (before capture edge) slave (after enable edge) (3) 3. assumes 200 pf load on all spi pins t v(m) t v(s) 0.25 ? ? 500 t cyc(m) ns 11 data hold time (outputs) master (after capture edge) slave (after enable edge) t ho(m) t ho(s) 0.25 0 ? ? t cyc(m) ns 12 rise time (20% v dd to 70% v dd , c l = 200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t rm t rs ? ? 200 2.0 ns s 13 fall time (70% v dd to 20% v dd , c l = 200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t fm t fs ? ? 200 2.0 ns s
electrical specifications technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 134 electrical specifications motorola figure 13-9. spi master timing diagram note note: this first clock edge is generated internally, but is not seen at the sck pin. ss pin of master held high. msb in ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) note 4 5 5 1 13 12 4 12 13 bits 6 ? 1 lsb in master msb out bits 6 ? 1 master lsb out 10 (ref) 13 11 10 12 11 (ref) 7 6 note note: this last clock edge is generated internally, but is not seen at the sck pin. ss pin of master held high. msb in ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) note 4 5 5 1 13 12 4 13 bits 6 ? 1 lsb in master msb out bits 6 ? 1 master lsb out 10 (ref) 13 11 10 12 11 7 6 12 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) 12
electrical specifications 3.3-v serial peripheral interface timing MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola electrical specifications 135 figure 13-10. spi slave timing diagram note: not defined but normally msb of character just received. slave ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (input) mosi (output) 4 5 5 1 13 12 4 13 msb in bits 6 ? 1 8 6 10 11 11 12 note slave lsb out 9 3 lsb in 2 7 bits 6 ? 1 msb out note: not defined but normally lsb of character previously transmitted. slave ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) 4 5 5 1 13 12 4 13 msb in bits 6 ? 1 8 6 10 11 12 note slave lsb out 9 3 lsb in 2 7 bits 6 ? 1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1)
electrical specifications technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 136 electrical specifications motorola
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola mechanical specifications 137 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a a mc68hcl05c8a mc68hsc05c8a section 14. mechanical specifications 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 14.3 40-pin plastic dual in-line (dip) package (case 711-03). . . . . . . . . . . . . . . . . . . . . . . . . . .138 14.4 42-pin plastic shrink dual in-line (sdip) package (case 858-01). . . . . . . . . . . . . . . . . . . . . . . . . . .138 14.5 44-lead plastic leaded chip carrier (plcc) (case 777-02). . . . . . . . . . . . . . . . . . . . . . 139 14.6 44-lead quad flat pack (qfp) (case 824a-01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 14.2 introduction this section describes the dimensions of the: dual in-line package (dip) plastic shrink dual in-line package (sdip) plastic leaded chip carrier (plcc) quad flat pack (qfp) mcu packages
mechanical specifications technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 138 mechanical specifications motorola 14.3 40-pin plastic dual in-line (dip) package (case 711-03) kage (case 711-03) 14.4 42-pin plastic shrink dual in-line (sdip) package (case 858-01) 120 40 21 b a c seating plane d f g h k n m j l dim min max min max inches millimeters a 51.69 52.45 2.035 2.065 b 13.72 14.22 0.540 0.560 c 3.94 5.08 0.155 0.200 d 0.36 0.56 0.014 0.022 f 1.02 1.52 0.040 0.060 g 2.54 bsc 0.100 bsc h 1.65 2.16 0.065 0.085 j 0.20 0.38 0.008 0.015 k 2.92 3.43 0.115 0.135 l 15.24 bsc 0.600 bsc m 1 n 0.51 1.02 0.020 0.040 notes: 1. position tolerance of leads (d), shall bewithin 0.25 (0.010) at maximum material conditions, in relation to seating plane and each other. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 1 0 0

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mechanical specifications 44-lead plastic leaded chip carrier (plcc) (case 777-02) MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola mechanical specifications 139 14.5 44-lead plastic leaded chip carrier (plcc) (case 777-02) -n- -l- -m- d y d k v w 1 44 brk b z u x view d-d s l-m m 0.007(0.180) n s t s l-m m 0.007(0.180) n s t g1 s l-m s 0.010 (0.25) n s t k1 f h s l-m m 0.007(0.180) n s t z g g1 r a e j view s c s l-m m 0.007(0.180) n s t s l-m m 0.007(0.180) n s t 0.004 (0.10) -t- seating plane view s dim min max min max millimeters inches a 0.685 0.695 17.40 17.65 b 0.685 0.695 17.40 17.65 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 0.51 k 0.025 0.64 r 0.650 0.656 16.51 16.66 u 0.650 0.656 16.51 16.66 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y 0.020 0.50 z 2 10 g1 0.610 0.630 15.50 16.00 k1 0.040 1.02 s l-m s 0.010 (0.25) n s t s l-m m 0.007(0.180) n s t 2 10 notes: 1. datums -l-, -m-, and -n- are determined where top of lead sholders exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimension r and u do not include mold flash. allowable mold flash is 0.010 (0.25) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are deter- mined at the outermost extremes of the plastic body exclusive of the mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. diminsion h does not include dambar protrusion or intrusion. the dambar protusion(s) shall not cause the h diminsion to be greater than 0.037 (0.940140). the dambar intrusion(s) shall not cause the h diminision to smaller than 0.025 (0.635).
mechanical specifications technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 140 mechanical specifications motorola 14.6 44-lead quad flat pack (qfp) (case 824a-01) 6 44-lead quad flat pack (qfp) (case 824a-01)
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MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola ordering information 141 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a sc05c8a section 15. ordering information 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 15.3 mcu ordering forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 15.4 application program media. . . . . . . . . . . . . . . . . . . . . . . . . . .142 15.5 rom program verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 15.6 rom verification units (rvus). . . . . . . . . . . . . . . . . . . . . . . . 143 15.2 introduction this section contains instructions for ordering custom-masked read-only memory (rom) microcontroller units (mcu). 15.3 mcu ordering forms to initiate an order for a rom-based mcu, first obtain the current ordering form for the mcu from a motorola representative. submit these items when ordering mcus: a current mcu ordering form that is completely filled out (contact your motorola sales office for assistance.) a copy of the customer specification if the customer specification deviates from the motorola specification for the mcu. customer ? s application program on one of the media listed in 15.4 application program media .
ordering information technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 142 ordering information motorola 15.4 application program media please deliver the application program to motorola in one of these media: macintosh ? (1) 3-1/2-inch diskette (double-sided 800 k or double-sided high-density 1.4 m) ms-dos ? (2) or pc-dos tm (3) 3-1/2-inch diskette (double-sided 720 k or double-sided high-density 1.44 m) ms-dos ? or pc-dos tm 5-1/4-inch diskette (double-sided double-density 360 k or double-sided high-density 1.2 m) use positive logic for data and addresses. when submitting the application program on a diskette, clearly label the diskette with this information: customer name customer part number project or product name file name of object code date name of operating system that formatted diskette formatted capacity of diskette on diskettes, the application program must be in motorola ? s s-record format (s1 and s9 records), a character-based object file format generated by m6805 cross assemblers and linkers. begin the application program at the first user rom location. program addresses must correspond exactly to the available on-chip user rom addresses as shown in the memory map. write $00 in all non-user rom locations or leave all non-user rom locations blank. refer to the current mcu ordering form for additional requirements. motorola may request pattern re-submission if non-user areas contain any non-zero code. 1. macintosh is a registered trademark of apple computer, inc. 2. ms-dos is a registered trademark of microsoft corporation. 3. pc-dos is a trademark of international business machines corporation.
ordering information rom program verification MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola ordering information 143 if the memory map has two user rom areas with the same addresses, then write the two areas in separate files on the diskette. label the diskette with both filenames. in addition to the object code, a file containing the source code can be included. motorola keeps this code confidential and uses it only to expedite rom pattern generation in case of any difficulty with the object code. label the diskette with the filename of the source code. 15.5 rom program verification verification the primary use for the on-chip rom is to hold the customer ? s application program. the customer develops and debugs the application program and then submits the mcu order along with the application program. motorola inputs the customer ? s application program code into a computer program that generates a listing verify file. the listing verify file represents the memory map of the mcu. the listing verify file contains the user rom code and may also contain non-user rom code, such as self-check code. motorola sends the customer a computer printout of the listing verify file along with a listing verify form. to aid the customer in checking the listing verify file, motorola will program the listing verify file into customer-supplied blank preformatted macintosh or dos disks. all original pattern media are filed for contractual purposes and are not returned. check the listing verify file thoroughly, then complete and sign the listing verify form and return the listing verify form to motorola. the signed listing verify form constitutes the contractual agreement for the creation of the custom mask. 15.6 rom verification units (rvus) after receiving the signed listing verify form, motorola manufactures a custom photographic mask. the mask contains the customer ? s application program and is used to process silicon wafers. the
ordering information technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 144 ordering information motorola application program cannot be changed after the manufacture of the mask begins. motorola then produces 10 mcus, called rvus, and sends the rvus to the customer. rvus are usually packaged in unmarked ceramic and tested to 5 vdc at room temperature. rvus are not tested to environmental extremes because their sole purpose is to demonstrate that the customer ? s user rom pattern was properly implemented. the 10 rvus are free of charge with the minimum order quantity. these units are not to be used for qualification or production. rvus are not guaranteed by motorola quality assurance.
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola mc68hcl05c8a 145 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a mc68hcl05c8a mc68hsc05c8a appendix a. mc68hcl05c8a a.1 contents a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 a.3 low-power operating temperature range . . . . . . . . . . . . . . 145 a.4 2.5-v to 3.6-v dc electrical characteristics . . . . . . . . . . . . . 146 a.5 1.8-v to 2.4-v dc electrical characteristics . . . . . . . . . . . . . . 146 a.6 low-power supply current . . . . . . . . . . . . . . . . . . . . . . . . . . 147 a.2 introduction this appendix introduces the mc68hcl05c8a, a low-power version of the MC68HC05C8A. the technical data applying to the MC68HC05C8A applies to the mc68hcl05c8a with the exceptions given here. a.3 low-power operating temperature range mperature range the follow data replaces the corresponding data found in 13.4 operating temperature range . rating symbol value unit operating temperature range (1) mc68hcl05c8ap, fn, b, fb 1. p = plastic dual in-line package (pdip) fn = plastic-leaded chip carrier (plcc) b = shrink dual in-line package (sdip) fb = quad flat pack (qfp) t a t l to t h 0 to +70 c
mc68hcl05c8a technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 146 mc68hcl05c8a motorola a.4 2.5-v to 3.6-v dc electrical characteristics a.5 1.8-v to 2.4-v dc electrical characteristics characteristic symbol min (1) 1. v dd = 2.5 ? 3.6 vdc typ max unit output high voltage (i load = ? 0.2 ma) pa7 ? pa0, pb7 ? pb0, pc6 ? pc0, tcmp (i load = ? 0.4 ma) pd4 ? pd1 (i load = ? 1.5 ma) pc7 v oh v dd ? 0.3 v dd ? 0.3 v dd ? 0.3 ? ? ? ? ? ? v output low voltage (i load = 0.4 ma) pa7 ? pa 0 , p b 7 ? pb0, pc6 ? pc0, pd4 ? pd1, tcmp (i load = 5.0 ma) pc7 v ol ? ? ? ? 0.3 0.3 v input pullup current pb7 ? pb0 (with pullup) i i n 40 160 300 a characteristic symbol min (1) 1. v dd = 2.5 ? 3.6 vdc typ max unit output high voltage (i load = ? 0.1 ma) pa7 ? pa0, pb7 ? pb0, pc6 ? pc0, tcmp (i load = ? 0.2 ma) pd4 ? pd1 (i load = ? 0.75 ma) pc7 v oh v dd ? 0.3 v dd ? 0.3 v dd ? 0.3 ? ? ? ? ? ? v output low voltage (i load = 0.2 ma) pa7 ? pa 0 , p b 7 ? pb0, pc6 ? pc0, pd4 ? pd1, tcmp (i load = 2.0 ma) pc7 v ol ? ? ? ? 0.3 0.3 v input pullup current pb7 ? pb0 (with pullup) i in 15 110 200 a
mc68hcl05c8a low-power supply current MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola mc68hcl05c8a 147 a.6 low-power supply current w-power supply current characteristic (1) 1. typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 c only. symbol min typ (1) max unit supply current (4.5 ? 5.5 vdc @ f bus = 2.1 mhz) run (2) wait (3) stop (4) 25 c 0 c to +70 c (standard) i dd ? ? ? ? 3.50 1.6 1 ? 4.25 2.25 15 25 ma ma a a supply current (2.4 ? 3.6 vdc @ f bus = 1.0 mhz) run (2) wait (3) stop (4) 25 c 0 c to +70 c (standard) 2. run (operating) i dd measured using external square wave clock source; all i/o pins configured as inputs, port b = v dd , all other inputs v il = 0.2 v, v ih = v dd ? 0.2 v; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2 3. wait i dd measured using external square wave clock source; all i/o pins configured as inputs, port b = v dd , all other inputs v il = 0.2 v, v ih = v dd ? 0.2 v; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2. wait i dd is affected linearly by the osc2 capacitance. 4. stop i dd measured with osc1 = 0.2 v; all i/o pins configured as inputs, port b = v dd , all other inputs v il = 0.2 v, v ih = v dd ? 0.2 v i dd ? ? ? ? 1.00 0.7 1 ? 1.4 1.0 5 10 ma ma a a supply current (2.5 ? 3.6 vdc @ f bus = 500 khz) run (2) wait (3) stop (4) 25 c 0 c to +70 c (standard) i dd ? ? ? ? 500 300 1 ? 750 500 5 10 a a a a supply current (1.8 ? 2.4 vdc @ f bus = 500 khz) run (2) wait (3) stop (4) 25 c 0 c to +70 c (standard) i dd ? ? ? ? 300 250 1 ? 600 400 2 5 a a a a
mc68hcl05c8a technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 148 mc68hcl05c8a motorola
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola mc68hsc05c8a 149 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a appendix b. mc68hsc05c8a b.1 contents b.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 b.3 high-speed operating temperature range. . . . . . . . . . . . . . 149 b.4 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 150 b.5 4.5-v to 5.5-v control timing . . . . . . . . . . . . . . . . . . . . . . . . . 151 b.6 2.4-v to 3.6-v control timing . . . . . . . . . . . . . . . . . . . . . . . . . 152 b.7 4.5-v to 5.5-v high-speed spi timing . . . . . . . . . . . . . . . . . . 153 b.8 2.4-v to 3.6-v high-speed spi timing . . . . . . . . . . . . . . . . . . 154 b.2 introduction duction this appendix introduces the mc68hsc05c8a, a high-speed version of the MC68HC05C8A. the technical data applying to the MC68HC05C8A applies to the mc68hsc05c8a with the exceptions given here. b.3 high-speed operating temperature range the follow data replaces the corresponding data found in 13.4 operating temperature range . rating symbol value unit operating temperature range (1) mc68hsc05c8ap, fn, b, fb mc68hsc05c8cp, cfn, cb, cfb 1. p = plastic dual in-line package (pdip) fn = plastic-leaded chip carrier (plcc) b = shrink dual in-line package (sdip) fb = quad flat pack (qfp) t a t l to t h 0 to +70 ? 40 to +85 c
mc68hsc05c8a technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 150 mc68hsc05c8a motorola b.4 dc electrical characteristics electrical characteristics the data in 13.7 5.0-v dc electrical characteristics and 13.8 3.3-v dc electrical characteristics applies to the mc68hsc05c8a with the exceptions given here. characteristic (1) symbol min typ max unit supply current (4.5 ? 5.5 vdc @ f bus = 4.0 mhz) run (2) wait (3) stop (4) 25 c 0 c to 70 c (standard) ? 40 c to 125 c (standard) i dd ? ? ? ? ? 7.00 2.00 1 ? ? 11.0 6.50 20 40 50 ma ma a a a supply current (2.4 ? 3.6 vdc @ f bus = 2.0 mhz) run (2) wait (3) stop (4) 25 c 0 c to 70 c (standard) ? 40 c to 125 c (standard) i dd ? ? ? ? ? 2.50 1.00 1 ? ? 4.00 2.00 8 16 20 ma ma a a a input pullup current (v dd = 4.5 ? 5.5 v) pb7 ? pb0 (with pullup) i in 175 385 750 a input pullup current (v dd = 2.4 ? 3.6 v) pb7 ? pb0 (with pullup) i in 50 160 350 a 1. typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 c only. 2. run (operating) i dd measured using external square wave clock source; all i/o pins configured as inputs, port b = v dd , all other inputs v il = 0.2 v, v ih = v dd ? 0.2 v; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2 3. wait i dd measured using external square wave clock source; all i/o pins configured as inputs, port b = v dd , all other inputs v il = 0.2 v, v ih = v dd ? 0.2 v; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2. wait i dd is affected linearly by the osc2 capacitance. 4. stop i dd measured with osc1 = 0.2 v; all i/o pins configured as inputs, port b = v dd , all other inputs v il = 0.2 v, v ih = v dd ? 0.2 v
mc68hsc05c8a 4.5-v to 5.5-v control timing MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola mc68hsc05c8a 151 b.5 4.5-v to 5.5-v control timing the data in 13.9 5.0-v control timing applies to the mc68hsc05c8a with the exceptions given here. characteristic symbol min max unit oscillator frequency crystal external clock f osc ? dc 8.2 8.2 mhz internal operating frequency (f osc 2) crystal external clock f op ? dc 4.1 4.1 mhz cycle time t cyc 244 ? ns crystal oscillator startup time t oxov 100 ms stop recovery startup time t ilch 100 ms reset pulse width t rl 1.5 ? t cyc timer resolution (1) input capture pulse width input capture pulse width t resl t th or t tl t thtl 4.0 64 (2) ? ? ? t cyc ns t cyc interrupt pulse width low (edge-triggered) t ilih 64 ? ns interrupt pulse period t ilil (3) ? t cyc osc1 pulse width t oh or t ol 50 ? ns 1. because a 2-bit prescaler in the timer must count four internal cycles ( t cyc ), this is the limiting minimum factor in deter- mining the timer resolution. 2. the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . 3. the minimum t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 t cyc .
mc68hsc05c8a technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 152 mc68hsc05c8a motorola b.6 2.4-v to 3.6-v control timing the data in 13.10 3.3-v control timing applies to the mc68hsc05c8a with the exceptions given here. characteristic symbol min max unit oscillator frequency crystal external clock f osc ? dc 4.2 4.2 mhz internal operating frequency (f osc 2) crystal external clock f op ? dc 2.1 2.1 mhz cycle time t cyc 480 ? ns crystal oscillator startup time t oxov 100 ms stop recovery startup time t ilch 100 ms reset pulse width t rl 1.5 ? t cyc timer resolution (1) input capture pulse width input capture pulse width t resl t th or t tl t thtl 4.0 125 (2) ? ? ? t cyc ns t cyc interrupt pulse width low (edge-triggered) t ilih 125 ? ns interrupt pulse period t ilil (3) ? t cyc osc1 pulse width t oh or t ol 90 ? ns 1. because a 2-bit prescaler in the timer must count four internal cycles ( t cyc ), this is the limiting minimum factor in deter- mining the timer resolution. 2. the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . 3. the minimum t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 t cyc .
mc68hsc05c8a 4.5-v to 5.5-v high-speed spi timing MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola mc68hsc05c8a 153 b.7 4.5-v to 5.5-v high-speed spi timing d spi timing the data in 13.11 5.0-v serial peripheral interface timing applies to the mc68hsc05c8a with the exceptions given here. num characteristic symbol min max unit operating frequency master slave f op(m) f op(s) dc dc 0.5 4.1 f op mhz 1 cycle time master slave t cyc(m) t cyc(s) 2.0 244 ? ? t cyc ns 2 enable lead time master slave t lead(m) t l ead(s) (1) 122 ? ? ns ns 3 enable lag time master slave t lag(m) t lag(s) (1) 366 ? ? ns ns 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s 166 93 ? ? ns ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s 166 93 ? ? ns ns 6 data setup time (inputs) master slave t su(m) t su(s) 49 49 ? ? ns ns 7 data hold time (inputs) master slave t h(m) t h(s) 49 49 ? ? ns ns 8 slave access time (time to data active from high-impedance state) t a 061 ns 9 slave disable time (hold time to high-impedance state) t dis ? 122 ns 10 data valid master (before capture edge) slave (after enable edge) (2) t v(m) t v(s) 0.25 ? ? 122 t cyc(m) ns 11 data hold time (outputs) master (after capture edge) slave (after enable edge) t ho(m) t ho(s) 0.25 0 ? ? t cyc(m) ns 12 rise time (20% v dd to 70% v dd , c l = 200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t rm t rs ? ? 50 1.0 ns s 13 fall time (70% v dd to 20% v dd , c l = 200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t fm t fs ? ? 50 1.0 ns s 1. signal production depends on software. 2. assumes 200 pf load on all spi pins.
mc68hsc05c8a technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 154 mc68hsc05c8a motorola b.8 2.4-v to 3.6-v high-speed spi timing the data in 13.12 3.3-v serial peripheral interface timing applies to the mc68hsc05c8a with the exceptions given in the following table. num characteristic symbol min max unit operating frequency master slave f op(m) f op(s) dc dc 0.5 2.1 f op mhz 1 cycle time master slave t cyc(m) t cyc(s) 2.0 480 ? ? t cyc ns 2 enable lead time master slave t lead(m) t lead(s) (1) 240 ? ? ns ns 3 enable lag time master slave t lag(m) t lag(s) (1) 720 ? ? ns ns 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s 340 190 ? ? ns ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s 340 190 ? ? ns ns 6 data setup time (inputs) master slave t su(m) t su(s) 100 100 ? ? ns ns 7 data hold time (inputs) master slave t h(m) t h(s) 100 100 ? ? ns ns 8 slave access time (time to data active from high-impedance state) t a 0120 ns 9 slave disable time (hold time to high-impedance state) t dis ? 240 ns 10 data master (before capture edge) slave (after enable edge) (2) t v(m) t v(s) 0.25 ? ? 240 t cyc(m) ns 11 data hold time (outputs) master (after capture edge) slave (after enable edge) t ho(m) t ho(s) 0.25 0 ? ? t cyc(m) ns 12 rise time (20% v dd to 70% v dd , c l = 200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t rm t rs ? ? 100 2.0 ns s 13 fall time (70% v dd to 20% v dd , c l = 200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t fm t fs ? ? 100 2.0 ns s 1. signal production depends on software. 2. assumes 20 pf load on all spi pins.
MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 technical data motorola m68hc05cx family feature comparisons 155 technical data ? MC68HC05C8A mc68hcl05c8a mc68hsc05c8a mc68hcl05c8a mc68hsc05c8a appendix c. m68hc05cx family feature comparisons y feature comparisons refer to table c-1 for a comparison of the features for all the m68hc05c family members.
technical data MC68HC05C8A mc68hcl05c8a mc68hsc05c8a ? rev. 5.0 156 m68hc05cx family feature comparisons motorola m68hc05cx family feature comparisons table c-1. m68hc05cx feature comparison c4 c4a 705c4a c8 c8a 705c8 705c8a c12 c12a c9 c9a 705c9 705c9a user rom 4160 4160 ? 7744 7744 ?? 12,096 12,096 15,760 ? 15,936 15,760 ? 15,936 ?? user eprom ?? 4160 ?? 7596 ? 7740 7596 ? 7740 ?? ? ? 15,760 ? 15,936 12,096 ? 15,936 code security no yes yes no yes yes yes no yes no yes no yes ram 176 176 176 176 176 176 ? 304 176 ? 304 176 176 176 ? 352 176 ? 352 176 ? 352 176 ? 352 option register (irq/ram/ sec) no no $1fdf (irq/sec) no no $1fdf (irq/ram/ sec) $1fdf (irq/ram/sec) no no $3fdf (irq/ram) $3fdf (irq/ram) $3fdf (irq/ram) $3fdf (irq/ram) mask option register(s) no no $1ff0 ? 1 no no no $1ff0 ? 1 no no no no no $3ff0 ? 1 portb keyscan (pullup/ interrupt) no yes mask option yes mor select- able no yes mask option no yes mor selectable yes mask option yes mask option no yes mask option no yes mor selectable pc7 drive standard high current high current standard high current standard high current high current high current standard high current standard high current port d pd7, 5 ? 0 input only pd7, 5 ? 0 input only pd7, 5 ? 0 input only pd7, 5 ? 0 input only pd7, 5 ? 0 input only pd7, 5 ? 0 input only pd7, 5 ? 0 input only pd7, 5 ? 0 input only pd7, 5 ? 0 input only pd7, 5 ? 0 bidirec- tional pd7, 5 ? 0 bidirec- tional pd7, 5 ? 0 bidirec- tional pd7, 5 ? 0 bidirectional cop no yes yes no yes yes two types yes yes yes yes yes two types cop enable ? mask option mor ? mask option software software+ mor mask option mask option software software software software+ mor cop timeout ? 64 ms (@4 mhz osc) 64 ms (@4 mhz osc) ? 64 ms (@4 mhz osc) software selectable software+ mor selectable 64 ms (@4 mhz osc) 64 ms (@4mhz osc) software selectable software selectable software selectable software+ mor selectable cop clear ? clr $1ff0 clr $1ff0 ? clr $1ff0 write $55/$aa to $001d write $55/$aa to $001d or clr $1ff0 clr $3ff0 clr $3ff0 write $55/$aa to $001d write $55/$aa to $001d write $55/$aa to $001d write $55/$aa to $001d or clr $3ff0 clock monitor no no no no no yes yes no no yes yes yes yes (c9a mode) active reset no no no no no cop/clock monitor program- mable cop/clock monitor no no por/cop/ clock monitor por/cop/ clock monitor por/cop/ clock monitor por/c9a cop/ clock monitor stop disable no mask option no no mask option no no mask option mask option no no no mor selectable (c12a mode) notes: 1. the expanded ram map (from $30 ? $4f and $100 ? $15f) available on the otp devices mc68hc705c8 and mc68hc705c8a is not available on the rom devices mc68hc05c8 and MC68HC05C8A. 2. the programmable cop available on the mc68hc705c8 and mc68hc705c8a is not available on the MC68HC05C8A. for rom compatibility , use the non-programmable cop.

how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu minato-ku, tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ? typical ? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ? ty p i c a l s ? must be validated for each customer application by customer ? s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2002 MC68HC05C8A/d

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